CC1110Fx / CC1111Fx
With the channel filter bandwidth set to
500 kHz, the signal should stay within 80% of
MDMCFG4.
MDMCFG4.CHANBW_E
00 01 10 11
812 406 203 102
CHANBW_M
500 kHz, which is 400 kHz. Assuming
915
00
01
10
11
MHz frequency and ±20 ppm frequency
uncertainty for both the transmitting device and
the receiving device, the total frequency
uncertainty is ±40 ppm of 915 MHz, which is
±37 kHz. If the whole transmitted signal
bandwidth is to be received within 400 kHz, the
transmitted signal bandwidth should be
maximum 400 kHz – 2·37 kHz, which is
326 kHz.
650 325 162
541 270 135
464 232 116
81
68
58
Table 63: Channel Filter Bandwidths [kHz]
(assuming fref = 26 MHz)
MDMCFG4.
MDMCFG4.CHANBW_E
The CC1110Fx/CC1111Fx supports channel filter
bandwidths shown in Table 63 and Table 64
respectively.
CHANBW_M
00
01
10
11
94
75
63
54
00
01
10
11
750 375 188
600 300 150
500 250 125
429 214 107
Table 64: Channel Filter Bandwidths [kHz]
(assuming fref = 24 MHz)
14.7 Demodulator, Symbol Synchronizer, and Data Decision
gain before the sync word is detected, and
FOCCFG.FOC_POST_K selects the gain after
the sync word has been found.
CC1110Fx/CC1111Fx contains an advanced and
highly configurable demodulator. Channel
filtering and frequency offset compensation is
performed digitally. To generate the RSSI level
(see section 14.10.3 for more information) the
signal level in the channel is estimated. Data
filtering is also included for enhanced
performance.
14.7.2 Bit Synchronization
The bit synchronization algorithm extracts the
clock from the incoming symbols. The
algorithm requires that the expected data rate
is programmed as described in Section 14.5
on page 190. Re-synchronization is performed
continuously to adjust for error in the incoming
symbol rate.
14.7.1 Frequency Offset Compensation
When using 2-FSK, GFSK, or MSK
modulation, the demodulator will compensate
for the offset between the transmitter and
receiver frequency, within certain limits, by
estimating the centre of the received data. This
value is available in the FREQEST status
register. Writing the value from FREQEST into
14.7.3 Byte Synchronization
Byte synchronization is achieved by
a
continuous sync word search. The sync word
is a 16 bit configurable field (can be repeated
to get a 32 bit) that is automatically inserted at
the start of the packet by the modulator in
transmit mode.The demodulator uses this field
to find the byte boundaries in the stream of
bits. The sync word will also function as a
system identifier, since only packets with the
correct predefined sync word will be received if
the sync word detection in RX is enabled in
register MDMCFG2 (see Section 14.10.1). The
sync word detector correlates against the user-
configured 16 or 32 bit sync word. The
correlation threshold can be set to 15/16,
16/16, or 30/32 bits match. The sync word can
be further qualified using the preamble quality
indicator mechanism described below and/or a
carrier sense condition. The sync word is
FSCTRL0.FREQOFF
the
frequency
synthesizer is automatically adjusted according
to the estimated frequency offset.
The tracking range of the algorithm is
selectable as fractions of the channel
bandwidth with the FOCCFG.FOC_LIMIT
configuration register.
If the FOCCFG.FOC_BS_CS_GATE bit is set,
the offset compensator will freeze until carrier
sense asserts. This may be useful when the
radio is in RX for long periods with no traffic,
since the algorithm may drift to the boundaries
when trying to track noise.
The tracking loop has two gain factors, which
affects the settling time and noise sensitivity of
the algorithm. FOCCFG.FOC_PRE_K sets the
SWRS033E
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