ADC101S051
ADC101S051 Converter Electrical Characteristics
(Notes 7, 9)
(Continued)
The following specifications apply for V
A
= +2.7V to 5.25V, f
SCLK
= 4 MHz to 10 MHz, f
SAMPLE
= 200 ksps to 500 ksps,
C
L
= 15 pF, unless otherwise noted.
Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25˚C.
Parameter
Conditions
Typical
Limits
40
60
400
Acquisition Time + Conversion Time
3
30
20
50
Units
Symbol
AC ELECTRICAL CHARACTERISTICS
DC
t
ACQ
t
QUIET
t
AD
t
AJ
SCLK Duty Cycle
Track/Hold Acquisition Time
Throughput Time
Aperture Delay
Aperture Jitter
f
SCLK
= 10 MHz
50
% (min)
% (max)
ns (max)
SCLK cycles
ns (min)
ns
ps
ADC101S051 Timing Specifications
The following specifications apply for V
A
= +2.7V to 5.25V, GND = 0V, f
SCLK
= 4 MHz to 10 MHz, C
L
= 25 pF,
f
SAMPLE
= 200 ksps to 500 ksps,
Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25˚C.
Symbol
t
CS
t
SU
t
EN
t
ACC
t
CL
t
CH
t
H
Parameter
Minimum CS Pulse Width
CS to SCLK Setup Time
Delay from CS Until SDATA TRI-STATE
®
Disabled (Note 11)
Data Access Time after SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
V
A
= +2.7V to +3.6V
V
A
= +4.75V to +5.25V
V
A
= +2.7V to +3.6V
V
A
= +4.75V to +5.25V
1
V
A
= +2.7V to +3.6V
V
A
= +4.75V to +5.25V
Conditions
Typical
Limits
10
10
20
40
20
0.4 x t
SCLK
0.4 x t
SCLK
7
5
25
5
25
5
Units
ns (min)
ns (min)
ns (max)
ns (max)
ns (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
µs
t
DIS
SCLK Falling Edge to SDATA High
Impedance (Note 13)
Power-Up Time from Full Power-Down
t
POWER-UP
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2:
All voltages are measured with respect to GND = 0V, unless otherwise specified.
Note 3:
When the input voltage at any pin exceeds the power supply (that is, V
IN
<
GND or V
IN
>
V
A
), the current at that pin should be limited to 10 mA. The 20
mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. The Absolute
Maximum Rating specification does not apply to the V
A
pin. The current into the V
A
pin is limited by the Analog Supply Voltage specification.
Note 4:
The absolute maximum junction temperature (T
J
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by T
J
max, the
junction-to-ambient thermal resistance (θ
JA
), and the ambient temperature (T
A
), and can be calculated using the formula P
D
max = (T
J
max − T
A
) /
θ
JA
. The values
for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5:
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through zero ohms.
Note 6:
Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8:
This is the frequency range over which the electrical performance is guaranteed. The device is functional over a wider range which is specified under
Operating Ratings.
Note 9:
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.
Note 10:
Minimum Quiet Time required by bus relinquish and the start of the next conversion.
Note 11:
Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V.
Note 12:
Measured with the timing test circuit shown in Figure 1 and defined as the time taken by the output signal to cross 1.0V or 2.0V.
Note 13:
t
DIS
is derived from the time taken by the outputs to change by 0.5V with the timing test circuit shown in Figure 1. The measured number is then adjusted
to remove the effects of charging or discharging the output capacitance. This means that t
DIS
is the true bus relinquish time, independent of the bus loading.
5
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