W681308
XXXX PRODUCT DESCRIPTION
After finished shift out the command bytes, the FSM will change to DATA state if the Data_enb ( 0x14A1[4]) is true, or run
back to IDLE state if the Data_enb is false.
Data
When FSM goes into Data state, the control logic start to shift out write data to external SPI device if SPI_RD (0x14A1[3]) is
false, or shift in read data from external SPI device if SPI_RD (0x14A1[3]) is true. In bidirection mode, the control logic will
ignore SPI_RD (0x14A1[3]) and start to shift in/out the read/write data from/to external SPI device. After finishing shift out/in
the data bytes, the FSM will go back to IDLE state and wait for next transition.
IDLE
DATA
CMD
14.4
FIFO and RAM of SPI
The SPI module takes up to 5 bytes Register to write the control command and takes the 256x8 bytes RAM to do the
Read/Write access FIFO. In Bidirectional mode, the 256x8 bytes RAM will separate into two 128x8 bytes sections. One
(ADDR: 0x00~7F) for keep the transmit data, and the other one (ADDR: 0x80~0xFF) for store the receive data. Once the
Bidirectional mode is enabled, the SPI module will automatic put receive data from ADDR: 0x80 instead of the ADDR: 0x00
as in the unidirectional mode. It supports two memory access methods:
FIFO like method
MCU always read/write the same register (0x14AC) with hardware control the memory read/write address, and increase the
read/write pointer automatically after each read/write. The current write and read pointer can be read at register 0x14AE and
0x14AF.
Direct access method
MCU can read/write any byte of the memory after setting the read (0x14AF)/write (0x14AE) pointer first.
14.5
Interrupt Sources
The SPI module supports two types of interrupt sources:
TX/RX finish interrupt
When TX/RX byte counts (0x14AD) = DATA_LEN.
Middle flag interrupt
When TX/RX byte counts (0x14AD) = 16 * INTR_CNT (0x14A3[7:4]).
For any other options, refer to the description of the specific registers in W681308 Design Guide.
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Rev1.2
NUVOTEM TALEMA [ NUVOTEM TALEMA ]
