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SM89S16R1_06 参数 Datasheet PDF下载

SM89S16R1_06图片预览
型号: SM89S16R1_06
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,具有64KB闪存和1KB RAM和RTC和ADC与PWM & PDWU嵌入式 [8-Bits Micro-controller With 64KB Flash ROM & 1KB RAM & RTC & ADC & PWM & PDWU embedded]
分类和应用: 闪存微控制器光电二极管
文件页数/大小: 29 页 / 695 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SyncMOS Technologies International, Inc.  
SM89S16R1  
8-Bits Micro-controller  
With 64KB Flash ROM & 1KB RAM & RTC & ADC & PWM & PDWU embedded  
Function Description  
The SM89S16R1 is a stand-alone high-performance microcontroller designed for use in many applications, such as  
LCD monitor, instrumentation, or high-end consumer applications.  
In addition to the 80C51 standard functions, the device provides a number of dedicated hardware functions for these  
applications.  
The SM89S16R1 is a control-oriented CPU with on-chip program and data memory. It can be extended with external  
data memory up to 64K bytes. For system requiring extra capability, the SM89S16R1 can be enhanced by using  
external memory and peripherals.  
The SM89S16R1 has two software selectable modes of saving power consumptionIDLE and POWER-DOWN. The  
IDLE mode freezes the CPU while allowing the RAM, timer, serial ports and interrupt system to continue functioning.  
The POWER-DOWN mode save the RAM contents but freezes the oscillator causing all other chip functions to be  
inoperative. The POWER-DOWN mode can be terminated by H/W reset, or by any one of the two external interrupt  
or RTCI function.  
CPU  
The CPU of SM89S16R1 is compatible to standard 80C51. The structure of this CPU is shown as FIGURE 11. It  
contains Instruction Register (IR), Instruction Decoder, and Program Counter (PC), Accumulator (ACC), B Register,  
and control logic. This CPU provides a 8-bits bi-direction bus to communicate with other blocks in the chip. The  
address and data are transferred through on the same 8-bits bus.  
PROG.  
ADDR.  
IRQ  
ACC  
CONTROL  
LOGIC  
PROGRAM  
RES  
CLK  
TMP2  
Timing & Reset  
ADDR.REGISTER  
TMP1  
BUFFER  
CTRL.  
BUS  
PROGRAM  
INSTRUCTION  
DECODER  
INCREMENT  
ALU  
SP  
PROGRAM  
COUNTER  
B
INSTRUCTION  
REGISTER  
Register  
PSW  
DPTR  
DATA  
IN/OUT  
PCON  
POWER CTRL.Signal  
Figure 11 The CPU structure  
CPU Timing  
The machine cycle consists of a sequence of 6 states, numbered S1 through S6. Each state time lasts for two oscillator  
periods. Thus a machine cycle takes 12 oscillator periods. Each state is divided into a PHASE 1 half and a PHASE2  
half. FIGURE 12 Shows relationships between oscillator, phase, and S1-S6.  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
Ver 2.1 SM89S16R1 08/2006  
13