SyncMOS Technologies International, Inc.
SM89S16R1
8-Bits Micro-controller
With 64KB Flash ROM & 1KB RAM & RTC & ADC & PWM & PDWU embedded
TA= -40℃ to +85℃
CL=100pF for Port0, ALE and /PSEN; CL=80pF for all other outputs unless otherwise specified.
Symbol
FIGURE
PARAMETER
MIN
MAX
UNIT
External Clock drive into XTAL1
tCLK
4
4
4
4
4
4
Xtal1 Period
40(1)
20
20
-
-
ns
ns
ns
ns
ns
Ns
tCLKH
tCLKL
tCLKR
tLLIV
tCYC
Xtal1 HIGH time
Xtal1 LOW time
XTAL1 rise time
XTAL1 fall time
-
-
10
10
-
-
Controller cycle time = tCLK / 4
3.33
NOTES:
1. Operating at 25MHz.
Symbol
FIGURE
PARAMETER
MIN
MAX
25
UNIT
Program Memory
1/tCLK
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
7
7
7
7
7
7
7
7
7
7
7
7
System clock frequency
3.0
MHz
ns
ALE pulse width
2tCLK-40
tCLK-40
tCLK-30
Address valid to ALE low
Address hold after ALE low
ALE LOW to valid instruction in
ALE LOW to /PSEN LOW
/PSEN pulse width
ns
ns
4tCLK-100
3tCLK-105
ns
tCLK-30
ns
3tCLK-45
ns
/PSEN LOW to valid instruction in
Input instruction hold after /PSEN
Input instruction float after /PSEN
Address to valid instruction in
/PSEN low to address float
ns
0
ns
tCLK -25
5tCLK-105
10
ns
ns
ns
Data Memory
tAVLL
8,9
8,9
8
Address valid to ALE LOW
Address hold after ALE LOW
/RD pulse width
tCLK-40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tLLAX
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
tCLK-35
6tCLK-100
6tCLK-100
9
/WR pulse width
8
/RD LOW to valid data in
Data hold after /RD
5tCLK-165
8
0
8
Data float after /RD
2tCLK-70
8tCLK-150
9tCLK-165
3tCLK+50
8
ALE LOW to valid data in
Address to valid data in
ALE LOW to /RD or /WR LOW
Address valid to /WR or /RD LOW
Data valid to /WR transition
Data before /WR
8
8,9
8,9
9
3tCLK-50
4tCLK-130
tCLK-50
9
7tCLK-150
tCLK-50
9
Data hold after /WR
8
/RD LOW to address float
/RD or /WR HIGH to ALE HIGH
0
8,9
tCLK-40
tCLK+40
UART
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
10
10
10
10
10
Serial port clock time
12tCLK
10tCLK-133
2tCLK-117
0
ns
ns
ns
ns
ns
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
10tCLK-133
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.1 SM89S16R1 08/2006
10
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
