SyncMOS Technologies Inc.
May 2001
SM8051/80952
I/O Ports Timing
T8
T6
T7
T5
T4
T3
T2
T1
T12
T11
T10
T7
T9
T8
T6
X1
sampled
inputs P0,P1
sampled
inputs P2,P3
Output by
current data
next data
Mov Px,Src
RxD at Serial Port
Shift Clock
sampled
(Mode 0)
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
70%Vdd
20%Vdd-0.1V
0.45V
TCLCX
TCHCL
TCHCX
TCLCH
Tm.I
External Program Memory Read Cycle
TPLPH
#PSEN
TLHLL
TAVLL
TLLPL
TPXIZ
TPXIX
ALE
TPLAZ
TLLAX
TPLIV
Instruction. IN
A0 - A7
A0 - A7
PORT 0
TAVIV
A8 - A15
A8 - A15
PORT 2
Specifications subject to change without notice,contact your sales representatives for the most recent information.
11/16
Ver 1.1
SM8051/8052 07/2005
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
