SyncMOS Technologies Inc.
May 2001
SM8051/80952
Program Memory Read Cycle Timing
T1
T11
T12
T10
T2
T9
T8
T2
T3
T4
T5
T6
T7
T12
T1
OSC
ALE
1
2
5
7
#PSEN
#RD,#WR
3
3
PORT2
PORT0
ADDRESS A15 - A8
6
ADDRESS A15 - A8
4
8
Float
A7 - A0
Float
A7 - A0
Float
Float
Float
INST in
INST in
Data Memory Write Cycle Timing
T12
T3
T10
T11
T1
T2
T9
T8
T7
T4
T5
T6
T2
T3
T1
T12
OSC
ALE
1
#PSEN
#WR
5
6
2
ADDRESS A15 - A8
PORT2
PORT0
2
4
3
ADDRESS
or Float
INST
Float
DATA OUT
A7 - A0
Specifications subject to change without notice,contact your sales representatives for the most recent information.
10/16
Ver 1.1
SM8051/8052 07/2005