SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
8.6
Timer 2 Register( TL2, TH2 )
Mnemonic: TL2
Address: CCh
7
6
5
5
4
4
3
2
2
1
1
0
Reset
00H
TL2[7:0]
Mnemonic: TH2
Address: CDh
7
6
3
0
Reset
00H
TH2[7:0]
8.7
Compare/Reload/Capture Registers( CRCL, CRCH )
Mnemonic: CRCL
Address: CAh
7
6
5
4
3
2
2
1
1
0
Reset
00H
CRCL[7:0]
Mnemonic: CRCH
Address: CBh
7
6
5
4
3
0
Reset
00H
CRCH[7:0]
8.8
Compare/Capture Register 1( CCL1, CCH1 )
Mnemonic: CCL1
Address: C2h
7
6
5
4
3
2
2
1
1
0
Reset
00H
CCL1[7:0]
Mnemonic: CCH1
Address: C3h
0
7
6
5
4
3
Reset
00H
CCH1[7:0]
8.9
Compare/Capture Register 2( CCL2, CCH2 )
Mnemonic: CCL2
Address: C4h
7
6
5
4
3
2
2
1
1
0
Reset
00H
CCL2[7:0]
Mnemonic: CCH2
Address: C5h
0
7
6
5
4
3
Reset
CCH2[7:0]
00H
8.10
Compare/Capture Register 3( CCL3, CCH3 )
Mnemonic: CCL3
Address: C6h
7
6
5
4
3
2
2
1
1
0
Reset
00H
CCL3[7:0]
Mnemonic: CCH3
Address: C7h
Reset
7
6
5
4
3
0
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
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