SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
is written by the USB host using interrupt transfers to endpoint 2. The Endpoint 2 data
FIFO is first – in – first – out.
Note: These registers are reading only during USB operation.
19.27 USB Endpoint 3 Data Register( EP3DATA )
Mnemonic: EP3DATA
Address: 93h
7
6
5
4
3
2
1
0
Reset
00H
EP3DATA[7:0]
EP3DATA[7:0]: Endpoint 3 Transmit FIFO data register
This register is used by the MCU to write data to the transmit FIFO. The FIFO is read by
the USB host using bulk transfers from endpoint 3. The Endpoint 3 data FIFO is first – in –
first – out.
Note: These registers are writing only during USB operation.
19.28 USB Endpoint 4 Data Register( EP4DATA )
Mnemonic: EP4DATA
Address: 94h
7
6
5
4
3
2
1
0
Reset
00H
EP4DATA[7:0]
EP4DATA[7:0]: Endpoint 4 received FIFO data register.
This register is used by the MCU to read data from the USB receive FIFO. The FIFO is
written by the USB host using bulk transfers to endpoint 4. The Endpoint 4 data FIFO is
first – in – first – out.
Note: These registers are reading only during USB operation.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
- 130 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
