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OB59A16U1U48VP 参数 Datasheet PDF下载

OB59A16U1U48VP图片预览
型号: OB59A16U1U48VP
PDF下载: 下载PDF文件 查看货源
内容描述: SM59A16U1 8位微控制器 64KB具有ISP闪存 & 6K + 256B RAM嵌入式 [SM59A16U1 8-Bit Micro-controller 64KB with ISP Flash & 6K+256B RAM embedded]
分类和应用: 闪存微控制器
文件页数/大小: 146 页 / 4372 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM59A16U1  
8-Bit Micro-controller  
64KB with ISP Flash  
& 6K+256B RAM embedded  
19.19 USB Endpoint 0 Data Counter Register( EP0CNT )  
Mnemonic: EP0CNT  
Address: B7h  
7
6
5
4
3
2
1
0
Reset  
00H  
-
EP0CNT[3:0]  
EP0CNT[3:0]:  
The EP0CNT is automatically incremented by 1 after the endpoint 0 receive FIFO register  
(EP0DATA) is written by SIE. The EP0CNT will count to 8H when it reaches the maximum  
count. The EP0CNT is automatically decreased by 1 after the MCU to read EP0DATA  
register. If EP0CNT = 00h, the Endpoint 0 FIFO is empty.  
When endpoint 0 transmit mailbox (EP0DATA) data port is written by MCU, the pointer is  
automatically incremented by 1. The EP1CNT will count to 8H when it reaches the  
maximum count.  
19.20 USB Endpoint 1 Data Counter Register( EP1CNT )  
Mnemonic: EP1CNT  
Address: A1h  
7
6
5
4
3
2
1
0
Reset  
-
EP1CNT[3:0]  
00H  
EP1CNT[3:0]:  
This register determines which address of endpoint 1 transmit register is accessed when  
the Endpoint 1 transmit mailbox (EP1DATA) data port is written by MCU. This pointer is  
automatically incremented by 1 after the endpoint 1 transmit mailbox data port is written by  
MCU. The EP1CNT will count to 8H when it reaches the maximum count.  
19.21 USB Endpoint 2 Data Counter Register( EP2CNT )  
Mnemonic: EP2CNT  
Address: A2h  
7
6
5
4
3
2
1
0
Reset  
00H  
-
EP2CNT[3:0]  
EP2CNT[3:0]:  
The EP2CNT is automatically incremented by 1 after the endpoint 2 receive FIFO register  
(EP2DATA) is written by SIE. The EP2CNT will count to 8H when it reaches the maximum  
count. The EP2CNT is automatically decreased by 1 after the MCU to read EP2DATA  
register. If EP2CNT = 00h, the Endpoint 2 FIFO is empty.  
19.22 USB Endpoint 3 Data Counter Register( EP3CNT )  
Mnemonic: EP3CNT  
Address: A3h  
7
-
6
5
4
3
2
1
0
Reset  
00H  
EP3CNT[6:0]  
EP3CNT[6:0]:  
Endpoint 3 device write data counter register.  
This register determines which address of endpoint 3 transmit register is accessed when  
the Endpoint 3 transmit FIFO (EP3DATA) data port is written by MCU. This EP3CNT is  
automatically incremented by 1 after the endpoint3 transmit FIFO data port is written by  
MCU. The EP3CNT pointer will count to 40H when it reaches the maximum count.  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
ISSFD-M071 Ver A SM59A16U1 04/12/2013  
- 128 -