SM59A16U1U48VP 参数 Datasheet PDF下载

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SM59A16U1

8-Bit Micro-controller

64KB with ISP Flash

& 6K+256B RAM embedded

Pin Configuration

48 Pin LQFP

P2.7/A15/KBI7/Op0Out(Cmp0Out)

P4.1/CC1/IIC_SDA/MOSI

P0.3/PWM3/KBI3/AD3

P0.4/AD4/KBI4/PWM4

P0.5/AD5/KBI5/PWM5

P0.6/AD6/KBI6/PWM6

P0.7/AD7/KBI7/PWM7

P2.5/A13/KBI5/Op0NIn

26

P2.6/A14/KBI6/Op0PIn

27

P4.6/OCI_SDA

36

35

34

33

32

31

30

29

28

25

P2.4/A12/KBI4/Op1PIn

P4.4/OCI_SCL

PWM2/KBI2/AD2/P0.2

PWM1/KBI1/AD1/P0.1

PWM0/KBI0/AD0/P0.0

VDD

AVDD_ADC

AVDDU

CAP

DM

DP

VSSALL

CC0/T2/ADC0/P1.0

CC1/T2EX/ADC1/P1.1

37

38

39

40

41

42

43

44

45

46

47

48

24

P2.3/A11/KBI3/Op1NIn/CC3

P2.2/A10/KBI2/Op1Out(Cmp1Out)/CC2

P2.1/A9/KBI1/CC1

P2.0/A8/KBI0/CC0

P4.5/ALE/CLKOUT

RESET

XTAL1

XTAL2

P3.0/RXD0

P3.1/TXD0

P3.2/INT0/TRIGADC

P3.3/INT1

59A16U1U48VP

IhhVP

yymmv

(48L LQFP Top View)

23

22

21

20

19

18

17

16

15

14

13

10

11

IIC_SDA/SPI_CLK/ADC7/P1.7

MOSI/ADC5/P1.5

IIC_SCL/MISO/ADC6/P1.6

SPI_CLK/TXD1/CC3/P4.3

MISO/RXD1/CC2/P4.2

RXD1/ADC2/P1.2

CC2/TXD1/ADC3/P1.3

CC3/SS/ADC4/P1.4

FLTB/RD/P3.7

FLTA/WR/P3.6

T1/P3.5

Notes：

(1)

To avoid accidentally entering ISP-Mode(refer to section 18.4), care must be taken not asserting pulse signal at

RXD P1.0 during power-up while P3.4 are set to high.

(2)

To apply ICP function, OCI_SDA/P4.6 and OCI_SCL/P4.4 must be set to Bi-direction mode if they are configured

as GPIO in system.

Specifications subject to change without notice contact your sales representatives for the most recent information.

ISSFD-M071

Ver A

SM59A16U1

04/12/2013

-8-

ADCEN/T0/P3.4

12

1

2

3

4

5

6

7

8

9