SyncMOS Technologies International, Inc.
SM5964
8-Bits Micro-controller
64KB ISP flash & 1KB RAM embedded
PDIV1
PDIV0
Divider
SPWM clock, Fosc=20MHz
SPWM clock, Fosc=24MHz
0
0
1
1
0
1
0
1
2
4
8
10MHz
5MHz
2.5MHz
1.25MHz
12MHz
6MHz
3MHz
16
1.5MHz
SPWM Data Register (SPWMD[4:0], $AC, $A7 ~$A4)
bit-7
bit-0
SPWMD
[4:0]4
R/W
SPWMD
[4:0]3
R/W
SPWMD
[4:0]2
R/W
SPWMD
[4:0]1
R/W
SPWMD
[4:0]0
R/W
BRM
BRM
BRM
[2:0]2
[2:0]1
[2:0]0
Read / Write:
Reset value:
R/W
0
R/W
0
R/W
0
0
0
0
0
0
SPWMD[4:0][4:0]: content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[4:0][2:0]: will insert certain narrow pulses among an 8-SPWM-cycle frame .
N = BRM[4:0][2:0]
Number of SPWM cycles inserted in an 8-cycle frame
XX1
X1X
1XX
1
2
4
Example of SPWM timing diagram:
MOV SPWMD0 , #83H
MOV P1CON , #08H
; SPWMD0[4:0]=10h (=16T high, 16T low), BRM[2:0] = 3
; Enable P1.3 as SPWM output pin
(narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)
SPWM clock = 1 / T = Fosc / 2^(PDIV +1)
The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(SPFS[1:0]+1)]/32
If user use Fosc=20MHz, SPFS[1:0] of SPWMC=#03H, then
SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz
SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.2 SM5964 08/2006
15
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
