SyncMOS Technologies International, Inc.
SM5964
8-Bits Micro-controller
64KB ISP flash & 1KB RAM embedded
4.1 Watch Dog Timer Registers: WDTC and SCONF
Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
bit-7
bit-0
WDTE
R/W
0
reserved**
Clear
R/W
0
Unused
Unused
PS2
R/W
0
PS1
R/W
0
PS0
R/W
0
Read / Write:
Reset value:
-
*
-
*
-
*
** Keep to “0” when write WDTC (9FH).
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer reset bit
PS[2:0] : Overflow period select bits
PS [2:0]
000
Divider(OSC in)
Time Period (ms) @ 40 MHZ
8
16
13.12.048
26.21
001
010
32
52.42
011
64
104.8
100
128
256
512
1024
209.71
419.43
838.86
1677.72
101
110
111
Watch Dog Timer Register - System Control Register (SCONF, $BF)
bit-7
bit-0
WDR
R/W
0
Unused
Unused
Unused
Unused
ISPE
R/W
0
OME
R/W
1
ALEI
R/W
0
Read / Write:
Reset value:
-
*
-
*
-
*
-
*
The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT
overflow. User should check WDR bit whenever un-predicted reset happened.
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.2 SM5964 08/2006
13
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
