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SM5964AL25 参数 Datasheet PDF下载

SM5964AL25图片预览
型号: SM5964AL25
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器,具有64KB ISP功能的Flash和TWSI与PWM和1KB RAM的嵌入式 [8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded]
分类和应用: 微控制器
文件页数/大小: 30 页 / 886 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SyncMOS Technologies International, Inc.
SM5964A
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
AC Characteristic
V
CC
=3.3V±10%, V
SS
=0V, t
clk
min = 1/ f
max
(maximum operating frequency)
T
A
=0
to +70℃
C
L
=100pF for Port0, ALE and /PSEN; C
L
=80pF for all other outputs unless otherwise specified.
Symbol
tCLK
tCLKH
tCLKL
tCLKR
tCLKF
tCYC
NOTES :
1.
Operating is 25MHz.
FIGURE
4
4
4
4
4
4
PARAMETER
External Clock drive into XTAL1
Xtal1 Period
Xtal1 HIGH time
Xtal1 LOW time
XTAL1 rise time
XTAL1 fall time
Controller cycle time = tCLK / 12
40(1)
20
20
-
-
3.33
MIN
MAX
-
-
-
10
10
-
ns
ns
ns
ns
ns
ns
UNIT
Symbol
1/tCLK
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
tAVLL
tLLAX
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tRLAZ
tWHLH
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
FIGURE
7
7
7
7
7
7
7
7
7
7
7
7
8,9
8,9
8
9
8
8
8
8
8
8,9
8,9
9
9
9
8
8,9
10
10
10
10
10
PARAMETER
Program Memory
System clock frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE LOW to valid instruction in
ALE LOW to /PSEN LOW
/PSEN pulse width
/PSEN LOW to valid instruction in
Input instruction hold after /PSEN
Input instruction float after /PSEN
Address to valid instruction in
/PSEN low to address float
Data Memory
Address valid to ALE LOW
Address hold after ALE LOW
/RD pulse width
/WR pulse width
/RD LOW to valid data in
Data hold after /RD
Data float after /RD
ALE LOW to valid data in
Address to valid data in
ALE LOW to /RD or /WR LOW
Address valid to /WR or /RD LOW
Data valid to /WR transition
Data before /WR
Data hold after /WR
/RD LOW to address float
/RD or /WR HIGH to ALE HIGH
UART
Serial port clock time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
MIN
3.0
2tCLK-40
tCLK-40
tCLK-30
tCLK-30
3tCLK-45
25
MAX
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4tCLK-100
3tCLK-105
0
tCLK -25
5tCLK-105
10
tCLK-40
tCLK-35
6tCLK-100
6tCLK-100
5tCLK-165
0
2tCLK-70
8tCLK-150
9tCLK-165
3tCLK+50
3tCLK-50
4tCLK-130
tCLK-50
7tCLK-150
tCLK-50
tCLK-40
12tCLK
10tCLK-133
2tCLK-117
0
0
tCLK+40
10tCLK-133
Specifications subject to change without notice contact your sales representatives for the most recent information.
9
Ver 2.3 SM5964A 10/2006