SyncMOS Technologies International, Inc.
SM5964A
8-Bit Micro-controller
With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded
repeat START condition
tSU;STA
STOP condition
START or repeat START condition
0.7VCC
0.3VCC
SDA
tFD
tRD
tHD;DAT
tFC
tBUF
tRC
tSP
START
tSU;STO
SCL
tSU;DAT3
tSU;DAT1
tSU;DAT2
tSU;DAT
tHIGH
tHD;STA
tLOW
Figure 11 Timing waveform of TWSI interface
Standard-MODE
Fast-MODE
Symbol
FIGURE
PARAMETER
UNIT
MIN
MAX
MIN
MAX
TWSI Bus
kHz
μS
fSCL
tBUF
11
11
SCL clock frequency
0
100
-
0
400
-
Bus free time between a stop and stop condition
4.7
1.3
Hold time (repeated) START condition. After this
period, the first clock pulse is generated
tHD;STA
11
4.0
-
0.6
-
μS
tLOW
11
11
11
11
11
11
11
Low Period of the SCL clock
High period of the SCL clock
Set-up time of a repeated START condition
Data hold time
4.7
4.7
4.0
0
-
1.3
1.3
0.6
0
-
μS
μS
μS
μS
nS
ns
tHIGH
-
-
tSU;STA
tHD;DAT
tSU;DAT
-
0
-
0.9
-
Data Setup-Time
250
-
-
100(1)
(2)
tRD, RC
t
Rise time of both SDA and SCL
Fall time of both SDA and SCL
1000
300
20+0.1Cb
300
300
(2)
tFD tFC
-
20+0.1Cb
ns
tSU;STO
tSU;STA
11
11
11
Set-up time for STOP and START condition
4.0
-
0.6
-
-
μS
pF
nS
Cb
Capacitive load for each bus line
-
-
400
-
400
50
Pulse width of spikes which must be suppressed by
input filter
tSP
0
NOTES:
1. A fast-mode TWSI bus device can be used in a standard-mode TWSI bus system, but the requirement tSU;DAT ≥ 250ns must the be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to SDA line tRMAX + tSU;DAT = 1000 + 250 = 1250 ns (according to the
standard-mode TWSI bus specification) before the SCL line is released.
2. Cb = Total capacitance of one bus line in pF.
Specifications subject to change without notice contact your sales representatives for the most recent information.
Ver 2.3 SM5964A 10/2006
12
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
