SyncMOS Technologies Inc.
May 2002
Block Diagram
Timer 2
Timer 1
Timer 0
Stack
Pointer
Decoder &
Register
1024 bytes
RAM
SM59264
WDT
RES
Reset
Circuit
to pertinent blocks
Acc
to whole chip
Buffer2
Buffer1
Buffer
DPTR
Vdd
Vss
Power
Circuit
PC
Incrementer
Interrupt
Circuit
to pertinent blocks
ALU
Program
Counter
XTAL2
XTAL1
#EA
ALE
#PSEN
Timing
Generator
to whole system
PSW
Register
Instruction
Register
1FFFFH
64KB
data flash
Port 0
Latch
SPWM
Port 1
Latch
Port 2
Latch
Port 3
Latch
Port 4
Latch
ISP
64KB
program
flash
10000H
4
2
0000H
Port 0
Driver & Mux
8
Port 1
Driver & Mux
8
Port 2
Driver & Mux
8
Port 3
Driver & Mux
8
Port 4
Driver & Mux
4
Specifications subject to change without notice,contact your sales representatives for the most recent information.
3/32
Ver 1.0
PID 59264 05/02
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
