SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Mnemonic: IICRWD
Address: FCh
7
6
5
4
3
2
1
0
Reset
00h
IICRWD[7:0]
IICRWD[7:0]: IIC read write data buffer.
In receiving (read) mode, the received byte is stored here.
In transmitting mode, the byte to be shifted out through SDA stays here.
Mnemonic: IICEBT
Address: FDH
7
6
5
-
4
-
3
-
2
-
1
-
0
-
Reset
00H
FU_EN
Master Mode：
00: reserved
01: IIC bus module will enable read/write data transfer on SDA and SCL.
10: IIC bus module generate a start condition on the SDA/SCL, then send out
address which is stored in the IICA1/IICA2(selected by MAS control bit)
11: IIC bus module generate a stop condition on the SDA/SCL.
Slave mode:
01: FU_EN[7:6] should be set as 01 only. The other value is inhibited.
Notice:
1. FU_EN[7:6] should be set as 01 before read/write data transfer for bus
release; otherwise, SCL will be locked(pull low).
2. FU_EN[7:6] should be set as 01 after read/write data transfer for receiving
a stop condition from bus master.
3. In transmit data mode (slave mode), the output data should be filled into
IICRWD before setting FU_EN[7:6] as 01.
4. FU_EN[7:6] will be auto-clear by hardware, so setting FU_EN[7:6]
repeatedly is necessary.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver B SM39R08A5 04/22/2013
- 45 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
