SM39R08A5
8-Bit Micro-controller
with 8KB Flash
& 256B RAM embedded
Mnemonic: RSTS
Address: A1h
7
-
6
-
5
-
4
3
2
1
0
Reset
00H
PDRF WDTF SWRF LVRF
PORF
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag
clear by software.
Mnemonic: WDTC
Address: B6h
7
-
6
5
4
-
3
2
1
0
Reset
04H
CWDTR WDTE
WDTM [3:0]
CWDTR: 0: watchdog reset
1: watchdog interrupt
WDTE: Control bit used to enable Watchdog timer.
The WDTE bit can be used only if WDTEN, the bit7 of information block OP3, is "0". If
the WDTEN bit is "0", then WDT can be disabled / enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if WDTEN, the bit7 of information block OP3, is "1". That is, if
the WDTEN bit is "1", WDT is always disabled no matter what the WDTE bit status is.
The WDTE bit can be read and written.
WDTM [3:0]: WDT clock source divider bit. Please see table 7.8.1 to reference the WDT time-out
period.
Mnemonic: WDTK
Address: B7h
7
6
5
4
3
2
1
0
Reset
00h
WDTK[7:0]
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog
timer will be cleared to zero.
For example, if enable WDT and select time-out reset period is 2.8493s.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
MOV WDTC, #28h
; enable WDTC write attribute.
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT
; function.
.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M067 Ver B SM39R08A5 04/22/2013
- 31 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
