SM39A16M1
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
SPIRST: SPI Re-start (Slave mode used only)
SPIRST = 0 - Re-start function disable.SPI Transmit/receive data when SS active.
In SPITXD/SPIRXD buffer, data got from previous SS active period will not be removed (i.e. it's valid).
SPIRST = 1 - Re-start function enable.SPI Transmit/receive new data when SS re-active;
In SPITXD/SPIRXD buffer, data got from previous SS active period will be removed (i.e. It's invalid).
TBC[2:0]: SPI Transmitter bit counter.
TBC[2:0]
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Bit counter
8 bits output
1 bit output
2 bits output
3 bits output
4 bits output
5 bits output
6 bits output
7 bits output
RBC[2:0]: SPI receiver bit counter.
RBC[2:0]
0:0:0
Bit counter
8 bits input
1 bit input
2 bits input
3 bits input
4 bits input
5 bits input
6 bits input
7 bits input
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Mnemonic: SPIS
Address:F5H
Reset
SPIRXIF SPIRDR SPIRS 40H
7
6
5
4
3
2
1
0
SPIRF
SPIMLS SPIOV SPITXIF SPITDR
SPIRF: SPI SS pin Release Flag.
This bit is set when SS pin release & SPIRST as „1‟.
SPIMLS: MSB or LSB first output /input Select.
SPIMLS = 1 is MSB first output/input.
SPIMLS = 0 is LSB first output/input.
SPIOV: Overflow flag.
When SPIRDR is set and next data already into shift register, this flag will be set.
It is clear by hardware, when SPIRDR is cleared.
SPITXIF: Transmit Interrupt Flag.
This bit is set when the data of the SPITXD register is downloaded to the shift register.
SPITDR: Transmit Data Ready.
When MCU finish writing data to SPITXD register, the MCU needs to set this bit to „1‟ to
inform the SPI module to send the data. After SPI module finishes sending the data
from SPITXD, this bit will be cleared automatically.
SPIRXIF: Receive Interrupt Flag.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M069
Ver C SM39A16M1 7/31/2013
- 87 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
