SM39A16M1
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
Mnemonic: WDTC
Address: B6h
7
-
6
5
4
-
3
2
1
0
Reset
04H
CWDTR
WDTE
WDTM [3:0]
CWDTR: Watch dog states select bit(Support stop mode wakeup)
CWDTR = 0 - Enable watch dog reset.
CWDTR = 1 - Enable watch dog interrupt.
WDTE: Control bit used to enable Watchdog timer.
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT
can be disabled / enabled by the WDTE bit.
WDTE = 0 - Disable WDT.
WDTE = 1 - Enable WDT.
The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is
always disabled no matter what the WDTE bit status is. The WDTE bit can be read
and written.
WDTM [3:0]:
WDT clock source divider bit. As seen in Fig. 10-1 to reference the WDT time-out
period.
Mnemonic: RSTS
Address: A1h
7
-
6
-
5
-
4
3
2
1
0
Reset
00h
PDRF WDTF SWRF
LVRF
PORF
WDTF:
Watchdog timer reset flag. When MCU is reset by watchdog, WDTF flag will be set to
one by hardware. This flag clear by software
Mnemonic: WDTK
Address: B7h
7
6
5
4
3
2
1
0
Reset
00h
WDTK[7:0]
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog
timer will be cleared to zero.
For example 1, if enable WDT and select time-out reset period is 2.8493s.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #0AAh
MOV TAKEY, #5Ah ; enable WDTC write attribute.
MOV WDTC, #28h
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT function.
.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M069 Ver C SM39A16M1 7/31/2013
- 56 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
