SM39A16M1
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
8.1.2 Event counter mode
In this mode, the timer is incremented when external signal T2 change value from 1 to 0. The T2 input is sampled in
every cycle. Timer 2 is incremented in the cycle following the one in which the transition was detected. As shown in Fig.
8-3.
Fig. 8-3: Event counter mode function
8.1.3 Gated timer mode
In this mode, the internal clock which incremented timer 2 is gated by external signal T2. As shown in Fig. 8-4
Fig. 8-4: Gated timer mode function
8.1.4 Reload of Timer 2
Reload (16-bit reload from the crc register) can be executed in the following two modes:
Mode 0: Reload signal is generate by a Timer 2 overflows - auto reload
Mode 1: Reload signal is generate by a negative transition at the corresponding input pin T2EX.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M069
Ver C SM39A16M1 7/31/2013
- 45 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
