SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
SM21: Enables multiprocessor communication feature.
REN1: If set, enables serial reception. Cleared by software to disable reception.
th
TB81:
The 9 transmitted data bit in mode A. Set or cleared by the CPU depending
on the function it performs such as parity check, multiprocessor
communication etc.
th
RB81:
TI1:
In mode A, it is the 9 data bit received. In mode B, if SM21 is 0, RB81 is the
stop bit. Must be cleared by software.
Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
RI1:
Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
9.5
Serial Port 1 Reload Register( S1RELL, S1RELH )
Mnemonic: S1RELL
Address: 9Dh
7
6
5
4
3
2
2
1
1
0
Reset
00h
S1REL[7:0]
Mnemonic: S1RELH
Address: BBh
7
6
5
4
3
0
Reset
00h
-
S1REL[9:8]
9.6
9.7
Serial Port 1 Data Buffer( S1BUF )
Mnemonic: S0BUF
Address: 9Ch
7
6
5
4
3
2
1
0
Reset
00h
S1BUF[7:0]
Serial Interface 0
The Serial Interface 0 can operate in the following 4 modes:
SM0
SM1
Mode
Description
Shift register
8-bit UART
9-bit UART
9-bit UART
Board Rate
0
0
1
1
0
1
0
1
0
1
2
3
Fosc/12
Variable
Fosc/32 or Fosc/64
Variable
Here Fosc is the crystal or oscillator frequency.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
- 65 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
