SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
Mnemonic: T2CON
Address: C8h
7
6
5
4
3
2
-
1
0
Reset
00H
T2PS[2:0]
T2R[1:0]
T2I[1:0]
T2PS[2:0]: Prescaler select bit:
T2PS = 000 – timer 2 is clocked with the oscillator frequency.
T2PS = 001 – timer 2 is clocked with 1/2 of the oscillator frequency.
T2PS = 010 – timer 2 is clocked with 1/4 of the oscillator frequency.
T2PS = 011 – timer 2 is clocked with 1/6 of the oscillator frequency.
T2PS = 100 – timer 2 is clocked with 1/8 of the oscillator frequency.
T2PS = 101 – timer 2 is clocked with 1/12 of the oscillator frequency.
T2PS = 110 – timer 2 is clocked with 1/24 of the oscillator frequency.
T2R[1:0]: Timer 2 reload mode selection
T2R[1:0] = 0X – Reload disabled
T2R[1:0] = 10 – Mode 0: Auto Reload
T2R[1:0] = 11 – Mode 1: T2EX Falling Edge Reload
T2I[1:0]: Timer 2 input selection
T2I[1:0] = 00 – Timer 2 stop
T2I[1:0] = 01 – Input frequency from prescaler (T2PS[2:0])
T2I[1:0] = 10 – Timer 2 is incremented by external signal at pin T2
T2I[1:0] = 11 – internal clock input is gated to the Timer 2
8.3
Compare/Capture Control Register( CCCON )
Mnemonic: CCCON
Address: C9h
7
6
5
4
3
2
1
0
Reset
00H
CCI3
CCI2
CCI1
CCI0
CCF3
CCF2
CCF1
CCF0
CCI3: Compare/Capture 3 interrupt control bit.
CCI3 = 1 is enable.
CCI2: Compare/Capture 2 interrupt control bit.
CCI3 = 1 is enable.
CCI1: Compare/Capture 1 interrupt control bit.
CCI3 = 1 is enable.
CCI0: Compare/Capture 0 interrupt control bit.
CCI3 = 1 is enable.
CCF3: Compare/Capture 3 flag set by hardware. This flag can be cleared by software.
CCF2: Compare/Capture 2 flag set by hardware. This flag can be cleared by software.
CCF1: Compare/Capture 1 flag set by hardware. This flag can be cleared by software.
CCF0: Compare/Capture 0 flag set by hardware. This flag can be cleared by software.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
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SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
