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59A16U1 参数 Datasheet PDF下载

59A16U1图片预览
型号: 59A16U1
PDF下载: 下载PDF文件 查看货源
内容描述: 带USB功能,内嵌64KB具有ISP功能的闪存和6K + 256B RAM的1T 8051控制器59A16U1 [带USB功能,内嵌 64KB具有 ISP 功能的 Flash和 6K+256B RAM的 1T 8051控制器59A16U1]
分类和应用: 闪存控制器
文件页数/大小: 146 页 / 4146 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM59A16U1  
8-Bit Micro-controller  
64KB with ISP Flash  
& 6K+256B RAM embedded  
8. Timer 2 and Capture Compare Unit  
Timer 2 is not only a 16-bit timer, also a 4-channel unit with compare, capture and reload functions. It is very similar to  
the programmable counter array (PCA) in some other MCUs except pulse width modulation (PWM).  
Timer 2 and capture compare module features:  
The timer 2 is 16-bit timer / counter.  
4-channel 16-bit compare / capture / reload functions.  
Comparator out can be CCU input source internally.  
Noise filter with CCU input.  
The timer 2 interrupt vector is 2Bh.  
Mnemonic  
Description  
Dir.  
Bit 7 Bit 6 Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0 RST  
Timer 2 and Capture Compare Unit  
CCU CCU  
AUX2  
Auxiliary 2 register  
92h  
-
2Sou 1Sou  
-
CCUINF[1:0]  
P42CC [1:0]  
T2I[1:0]  
00H  
00H  
rce  
rce  
T2CON  
CCCON  
Timer 2 control  
Compare/Capture  
Control  
C8h  
C9h  
T2PS[2:0]  
T2R[1:0]  
-
CCI3 CCI2 CCI1 CCI0  
CCF3  
CCF2  
CCF1 CCF0 00H  
Compare/Capture  
Enable register  
CCEN  
C1h  
D1h  
-
COCAM1[2:0]  
COCAM3[2:0]  
-
-
COCAM0[2:0]  
COCAM2[2:0]  
00H  
00H  
Compare/Capture  
Enable 2 register  
Timer 2, low byte  
Timer 2, high byte  
Compare/Reload/Cap  
ture register, low byte  
Compare/Reload/Cap  
CCEN2  
-
TL2  
TH2  
CCh  
CDh  
TL2[7:0]  
TH2[7:0]  
00H  
00H  
00H  
CRCL  
CAh  
CRCL[7:0]  
00H  
CRCH  
ture register, high CBh  
byte  
CRCH[7:0]  
Compare/Capture  
register 1, low byte  
Compare/Capture  
register 1, high byte  
Compare/Capture  
register 2, low byte  
Compare/Capture  
register 2, high byte  
Compare/Capture  
register 3, low byte  
Compare/Capture  
register 3, high byte  
00H  
00H  
00H  
00H  
00H  
00H  
CCL1  
CCH1  
CCL2  
CCH2  
CCL3  
CCH3  
C2h  
CCL1[7:0]  
CCH1[7:0]  
CCL2[7:0]  
CCH2[7:0]  
CCL3[7:0]  
CCH3[7:0]  
C3h  
C4h  
C5h  
C6h  
C7h  
8.1  
Auxiliary 2 Register( AUX2 )  
Mnemonic: AUX2  
Address: 92h  
7
6
5
4
3
2
1
0
Reset  
CCU2  
Source Source  
CCU1  
-
CCUINF[1:0]  
P42CC [1:0]  
00H  
The following Fig. 8-1 is set CCU action  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
ISSFD-M071 Ver A SM59A16U1 04/12/2013  
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