SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
mailbox registers. UIFR1 bit 2 is then set which can cause a local bus interrupt to signaling MCU check the EPDRDY
bit 3 (endpoint 2 received data ready) is set or not. If this bit is set, MCU can read the data from endpoint 2 safely. After
MCU completed read stage, it should be cleared the EPDRDY bit 3. Then it can wait until the next packet complete
interrupt, and read the entire packet once again. If the USB host tries to write to these registers when the EPDRDY bit
3 is set, a NAK acknowledge will be returned, signaling host that the next data packet could not be accepted.
19.4
USB Bulk Transfer From Host to Device
For host to device transfers, the host first arranges to transfer a block of data from host memory to local shared
memory. The USB host performs a bulk-out data transfer over the USB bus to the receive FIFO endpoint 4 in the MCU.
After MCU completed receive data, an interrupt will be generated to signaling MCU check the status register. For
example, MCU program should be check EPDRDY bit 5 (endpoint 4 received data ready) is set or not. If this bit is set,
MCU can read the data from endpoint 4 safely. After MCU completed read step, it should be cleared EPDRDY bit 5.
Then it can wait until the next packet complete interrupt, and read the entire packet once again. If the data ready
control bit (EPDRDY bit 5) from the previous packet is not cleared, then the MCU will return a USB NAK acknowledge
to the host, signaling that the next data packet could not be accepted.
The MCU can also read handshake status register to detect whether the packet was acknowledged with an ACK, NAK.
If these acknowledge bits are set, then a timeout has occurred. For NAK or timeout conditions at the completion of bulk
transfers, the USB host will send another OUT token, and MCU should receive the same packet again.
19.5
USB Bulk Transfer From Device to Host
For device to host transfers, the MCU first writes the data block from local memory into the transmit FIFO endpoint 3.
While writing data into the endpoint 3, the MCU must keep track of whether there is space available in the FIFO by
monitoring the index write pointer. After the block has been loaded into the transmit FIFO, the MCU should be set the
transmit flag (EPDRDY bit 4, endpoint 3 transmitted data ready) to notify SIE that FIFO data ready. The USB host
sends an IN token to the MCU and starts a USB bulk-in transfer, SIE will fetch endpoint 3 data and transfer data to host.
When the transmit FIFO becomes empty, the SIE will terminate the packet with an End Of Packet, signaling that there
is no more data available. Once an end of packet occurs, an interrupt can be generated to the MCU. The MCU can
read handshake status register to detect whether the packet was acknowledge with ACK from the host, or whether the
MCU respond to the IN token with a NAK.
If these acknowledge bits are set, then a timeout has occurred. For NAK or timeout conditions at the completion of bulk
transfers, the USB host will send another IN token, and the MCU should re-transmit the same packet.
USB Module Features:
Low speed (1.5Mbps) or Full speed (12Mbps).
Supports control, interrupt and bulk transfer.
Five endpoints with FIFO:
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EP0: Control IN/OUT. FIFO: 8 bytes
EP1: Interrupt IN. FIFO: 8 bytes.
EP2: Interrupt OUT. FIFO: 8 bytes.
EP3: Bulk IN. FIFO: 64 bytes.
EP4: Bulk OUT. FIFO: 64 bytes.
The USB interrupt vector is 73h.
The USBRSM interrupt vector is 7Bh.
Note: Crystal should be 6, 12 or 24MHz to use USB device controller stably.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071
Ver A SM59A16U1 04/12/2013
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SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
