SM59A16U1
8-Bit Micro-controller
64KB with ISP Flash
& 6K+256B RAM embedded
When ADJUST = 0, the ADC data format 1 as below:
Mnemonic: ADCDH
Address: ADh
7
6
5
4
3
2
1
0
Reset
ADCD[9] ADCD[8] ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] 00H
Mnemonic: ADCDL
Address: AEh
7
6
5
4
3
2
1
0
Reset
00H
-
ADCD[1] ADCD[0]
When ADJUST = 1, the ADC data format 2 as below:
Mnemonic: ADCDH
Address: ADh
Rese
7
6
5
4
3
2
1
0
ADCD[8]
t
-
ADCD[9]
00H
Mnemonic: ADCDL
Address: AEh
7
6
5
4
3
2
1
0
Reset
ADCD[7] ADCD[6] ADCD[5] ADCD[4] ADCD[3] ADCD[2] ADCD[1] ADCD[0] 00H
18.4
ADC Clock Select( ADCCS )
Mnemonic: ADCCS
Address: AFh
7
6
5
4
3
2
1
0
Reset
OP0
ToADC
ADCEN
ToP34
-
ADCCS[4:0]
00H
OP0ToADC: Select ADC channel 8 as input source
0 = Set ADC input source as decided by ADCC2.
1 = Set ADC input source as Op0 output.
ADCENToP34: ADC internal signal test and monitor.
0 = Disable ADC internal signal output to P3.4
1 = Enable ADC internal signal output to P3.4
ADCCS[4:0]: ADC clock select.
Fosc
ADC _Clock
2(ADCCS 1)
ADC_Clock
ADC _Conversion_ Rate
13
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M071 Ver A SM59A16U1 04/12/2013
- 116 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
