HV9110/HV9112/HV9113
Truth Table
Shutdown
Reset
Output
Normal Operation
H
H
H
H → L
Normal Operation, No Change
Off, Not Latched
L
L
H
L
L
Off, Latched
L → H
Off, Latched, No Change
Shutdown Timing Waveforms
tF ≤ 10ns
1.5V
V
DD
50%
50%
Sense
Shutdown
Output
tR ≤ 10ns
0
0
t
t
SD
d
V
V
DD
DD
90%
90%
Output
0
0
t
SW
V
DD
50%
50%
Shutdown
Reset
tR, tF ≤ 10ns
0
t
LW
V
DD
50%
50%
50%
0
t
RW
Functional Block Diagram
OSC
In
OSC
Out
FB
COMP
Discharge
14
(19)
13
(18)
9
(12)
8 (11)
7 (10)
Error
Amplifier
OSC
–
10 (14)
To V
+
DD
V
2V
T
Q
Modulator
Comparator
REF
–
+
+
–
4V
R
Q
S
4 (6)
Output
REF
GEN
9113
9110
9112
5 (8)
Current Limit
Comparator
-V
IN
To
Internal
Circuits
1 (20)
Current
Sources
1.2V
BIAS
3 (5)
Current Sense
6 (9)
2 (3)
V
DD
V
DD
11 (16)
Undervoltage
Comparator
–
Shutdown
Reset
S
+V
IN
Q
+
R
8.1V
8.6V
–
12 (17)
+
Pre-regulator/Startup
Pin numbers in parentheses are for PLCC package
4
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