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HV57708_07 参数 Datasheet PDF下载

HV57708_07图片预览
型号: HV57708_07
PDF下载: 下载PDF文件 查看货源
内容描述: 32MHz的64通道串行到并行转换器,具有推挽输出 [32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs]
分类和应用: 转换器
文件页数/大小: 7 页 / 670 K
品牌: SUPERTEX [ Supertex, Inc ]
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HV57708  
DC Electrical Characteristics(Over operating supply voltages and temperature, unless otherwise noted)  
Symbol Parameter  
IDD VDD supply current  
Min  
Max  
15  
Units Conditions  
-
mA  
µA  
µA  
µA  
V
VDD = VDD max, fCLK = 8MHz  
-
100  
100  
100  
-
Outputs high  
Outputs low  
All VIN = VDD  
IPP  
IDDQ  
VOH  
High voltage supply current  
-
Quiescent VDD supply current  
-
HVOUT  
High level output  
DOUT  
65  
IO = -15mA, VPP = +80V  
IO = -100µA  
VDD - 0.5V  
-
V
HVOUT  
Low level output  
DOUT  
-
-
-
-
-
7.0  
0.5  
1.0  
-1.0  
1.0  
V
IO = 12mA, VPP = +80V  
IO = 100µA  
VOL  
V
IIH  
IIL  
High-level logic input current  
Low-level logic input current  
High voltage clamp diode  
µA  
µA  
V
VIH = VDD  
VIL = 0V  
VOC  
IOC = 1.0mA  
AC Electrical Characteristics (TA = 85°C max. Logic signal inputs and Data inputs have tr, tf ≤ 5ns [10% and 90% points])  
Symbol Parameter  
Min  
Max  
Units Conditions  
fCLK  
tWL, tWH  
tSU  
Clock frequency  
-
8
MHz Per register  
Clock width high or low  
62  
10  
15  
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
---  
Data set-up time before clock rises  
Data hold time after clock rises  
-
-
---  
tH  
---  
tON, tOFF Time from latch enable to HVOUT  
500  
70  
70  
-
CL = 15pF  
CL = 15pF  
CL = 15pF  
---  
tDHL  
tDLH  
Delay time clock to data high to low  
Delay time clock to data low to high  
Delay time clock to LE low to high  
LE pulse width  
-
-
tDLE  
tWLE  
tSLE  
*
25  
25  
0
-
---  
LE set-up time before clock rises  
-
---  
* tDLE is not required but is recommended to produce stable HV outputs and thus minimize power dissipation and current spikes (allows internal SR  
output to stabilize).  
3
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