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HV57708_07 参数 Datasheet PDF下载

HV57708_07图片预览
型号: HV57708_07
PDF下载: 下载PDF文件 查看货源
内容描述: 32MHz的64通道串行到并行转换器,具有推挽输出 [32MHz, 64-Channel Serial to Parallel Converter with Push-Pull Outputs]
分类和应用: 转换器
文件页数/大小: 7 页 / 670 K
品牌: SUPERTEX [ Supertex, Inc ]
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HV57708  
Ordering Information  
Package Options  
80-Lead PQFP  
HV57708PG-G  
Device  
HV57708  
-G indicates package is RoHS compliant (‘Green’)  
Pin Configuration  
Absolute Maximum Ratings  
Parameter  
Value  
-0.5V to +7.5V  
-0.5V to +90V  
-0.3V to VDD + 0.3V  
1.5A  
Supply voltage, VDD  
Output voltage , VPP  
Logic input levels  
Ground current(1)  
Continuous total power dissipation(2)  
Operating temperature range  
Storage temperature range  
1200mW  
-40°C to +85°C  
-65°C to +150°C  
80  
1
Lead temperature 1.6mm from case  
for 10 seconds  
260°C  
80-Lead PQFP (PG)  
(top view)  
Absolute Maximum Ratings are those values beyond which damage to the  
device may occur. Functional operation under these conditions is not implied.  
Continuous operation of the device at the absolute rating level may affect  
device reliability. All voltages are referenced to device ground.  
Product Marking  
Top Marking  
Notes:  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
L = Lot Number  
1. Limited by the total dissipated in the package.  
2. For operation above 25°C ambient derate linearly to maximum  
operating temperature at 20mW/°C.  
HV57708PG  
LLLLLLLLLL  
C = Country of Origin*  
A = Assembler ID*  
Bottom Marking  
CCCCCCCC  
AAA  
= “Green” Packaging  
*May be part of top marking  
80-Lead PQFP (PG)  
Recommended Operating Conditions  
Symbol  
VDD  
VPP  
Parameter  
Min  
Max  
5.5  
80  
Units  
V
Logic supply voltage  
Output voltage  
4.5  
8.0  
V
VIH  
High-level input voltage  
Low-level input voltage  
Clock frequency per register  
Operating free-air temperature  
VDD - 0.5V  
-
V
VIL  
0
-
0.5  
8.0  
+85  
V
fCLK  
MHz  
°C  
TA  
-40  
Notes:  
Power-up sequence should be the following*:  
1. Apply ground  
2. Apply VDD  
3. Set all inputs (DIN, CLK, LE , POL, etc.) to a known state  
4. Apply VPP  
5. The VPP should not drop below VDD or float during operation  
Power-down sequence should be the reverse of the above  
2