HV57009
Switching Waveforms
VDD
VSS
VDD
Data Input
50%
Data Valid
50%
50%
tf
tr
tSU
tH
90%
50%
90%
50%
CLK
50%
10%
10%
VSS
tWL
tWH
VDD
VSS
50%
50%
tDLH
Data Out
VDD
VSS
tDHL
VDD
VSS
50%
50%
LE
tWLE
tSLE
tDLE
VDD
90%
HVOUT
w/ data input
LOW
Previous IO = IREF
10%
HVOUT (off)
IO = 0
tOFF
VDD
HVOUT
w/ data input
HIGH
90%
I
O = IREF
10%
tON
HVOUT (off)
Previous IO = 0
Function Table
Function
Inputs
Outputs
Data In
CLK
LE
BL
DIR
Shift Reg
HV Outputs
Data Out
All O/P high
X
L
X
X
H
H
L
L
H
H
H
H
H
H
H
X
X
X
X
H
H
L
*
ON
ON
*
_
_↑
_↑
L.....L
L
Data falls through
(latches transparent)
_
H
X
H.....H
*
OFF
H
Data stored in latches
X
Inversion of stored data
New ON or OFF
*
_
_
_
_
DI/O1-2A _↑
DI/O1-2A _↑
DI/O1-2B _↑
DI/O1-2B _↑
H
L
Qn→Qn+1
Qn→Qn+1
Qn→Qn-1
Qn→Qn-1
DI/O1-2B
DI/O1-2B
DI/O1-2A
DI/O1-2A
Previous ON or OFF
Previous ON or OFF
New ON or OFF
I/O relation
L
H
L
Note:
* = dependent on previous stage’s state. See Figure 7 for DIN and DOUT pin designation for CW and CCW shift.
H = VDD (Logic)/VNN (HV Outputs)
L = VSS
5
SUPERTEX [ Supertex, Inc ]
