HV57009
Switching Waveforms
V
DD
Data Input
50%
t
SU
CLK
50%
t
WL
50%
t
WH
50%
V
SS
Data Out
t
DLH
50%
t
DHL
V
DD
V
SS
Data Valid
t
H
90%
50%
50%
V
SS
t
f
t
r
V
DD
10%
10%
90%
50%
V
SS
V
DD
LE
t
DLE
50%
t
WLE
50%
t
SLE
V
DD
V
SS
HV
OUT
w/ data input
LOW
Previous I
O
= I
REF
t
OFF
90%
10%
I
O
= 0
V
DD
HV
OUT
(off)
HV
OUT
w/ data input
HIGH
10%
Previous I
O
= 0
t
ON
90%
I
O
= I
REF
V
DD
HV
OUT
(off)
Function Table
Inputs
Function
Data In
X
L
H
X
DI/O1-2A
I/O relation
DI/O1-2A
DI/O1-2B
DI/O1-2B
CLK
X
_
_↑
_
_↑
X
_
_↑
_
_↑
_
_↑
_
_↑
LE
X
H
H
L
H
L
L
H
BL
L
H
H
H
H
H
H
H
DIR
X
X
X
X
H
H
L
L
Shift Reg
*
L.....L
H.....H
*
Q
n
→Q
n+1
Q
n
→Q
n+1
Q
n
→Q
n-1
Q
n
→Q
n-1
Outputs
HV Outputs
ON
ON
OFF
Inversion of stored data
New ON or OFF
Previous ON or OFF
Previous ON or OFF
New ON or OFF
Data Out
*
L
H
*
DI/O1-2B
DI/O1-2B
DI/O1-2A
DI/O1-2A
All O/P high
Data falls through
(latches transparent)
Data stored in latches
Note:
* = dependent on previous stage’s state. See Figure 7 for DIN and DOUT pin designation for CW and CCW shift.
H = V
DD
(Logic)/V
NN
(HV Outputs)
L = V
SS
5
SUPERTEX [ Supertex, Inc ]
