HV57009
DC Electrical Characteristics(All voltages are referenced to VSS, VSS = 0, TA = 25OC)
Symbol Parameter
IDD VDD supply current
INN
Min
Max
Units Conditions
-
15
mA
VDD = VDD max, fCLK = 8.0MHz
Outputs off, HV = -85V
(total of all outpOuUtsT )
High voltage supply current
Quiescent VDD supply current
-
-
-10
µA
All inputs = V ,
except +IN = DVDSS = GND
IDDQ
VOH
100
µA
Data Out
VDD - 0.5V
-
V
V
IO = -100µA
IO = -2.0mA
IO = 100µA
VIH = VDD
High level output
Low level output
HVOUT
+1.0
VDD
+0.5
1.0
VOL
IIH
Data Out
-
-
-
V
High-level logic input current
Low-level logic input current
µA
µA
IIL
-1.0
VIL = 0V
V
REF = 2.0V, REXT = 1K,
see Figures 1a and 1b
REF = 0.1V, REXT = 1K,
-
-2.0
mA
ICS
High output source current
V
-0.1
-
-
mA
%
see Figures 1a and 1b
ΔICS
HV output source current for IREF = 2.0mA
10
VREF = 2.0V, REXT = 1K
Note:
Current going out of the chip is considered negative.
AC Electrical Characteristics(Logic signal inputs and data inputs have tr, tf ≤ 5ns [10% and 90% points] for measurements)
Symbol Parameter
Min
Max
Units Conditions
8.0
Per register
MHz
fCLK
Clock frequency
DC
4.5
When cascading devices
tWL, tWH
tSU
Clock width high or low
62
20
15
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
---
Data set-up time before clock rises
Data hold time after clock rises
-
---
tH
-
500
150
150
-
---
tON, tOFF Time from latch enable to HVOUT
CL = 15pF
CL = 15pF
CL = 15pF
---
tDHL
tDLH
tDLE
tWLE
tSLE
Delay time clock to data high to low
Delay time clock to data low to high
Delay time clock to LE low to high
LE pulse width
-
-
45
25
0
-
---
LE set-up time before clock rises
-
---
Max. allowable clock rise and fall time
(10% and 90% points)
tr, tf
-
100
ns
---
3
SUPERTEX [ Supertex, Inc ]
