Block Diagram
V
PP1
Current
Sense
and
Driver
Linear
Reg
V
psen
HV440
V
DD
P
IN
N
IN
EN
Mode
GND
High
Voltage
Level
Translator
P
gate
V
PP2
HV
OUT
Logic
V
DD
High
Voltage
Level
Translator
Linear
Reg
Current
Sense
and
Driver
P
GND
V
NN2
N
gate
V
nsen
V
NN1
Pin Description
V
PP1
V
PP2
V
NN1
V
NN2
V
DD
GND
PGND
P
IN
N
IN
EN
Mode
HV
OUT
V
psen
V
nsen
P
gate
N
gate
Positive high voltage supply.
Positive gate voltage supply. Generated by an internal linear regulator. A 0.1µF capacitor should be connected between V
PP2
and V
PP1
.
Negative high voltage supply.
Negative gate voltage supply. Generated by an internal linear regulator. A 0.1µF capacitor should be connected between V
NN2
and V
NN1
.
Logic supply voltage.
Low voltage ground.
High voltage power ground.
Logic control input. When mode is high, logic input high turns OFF output high voltage P-Channel.
Logic control input. When mode is high, logic input high turns ON output high voltage N-Channel.
Logic enable bar input. Logic low enables IC.
Logic mode input. Logic low activates 200nsec deadband. When mode is low, N
IN
turns on and off the high voltage N- and
P-Channels. Pin is not used and should be connected to V
DD
or ground.
High voltage output. Voltage swings from V
PP1
to V
NN1
.
Pulse by pulse over current sensing for internal P-Channel MOSFET.
Pulse by pulse over current sensing for internal N-Channel MOSFET.
Gate drive for external P-channel MOSFET.
Gate drive for external N-channel MOSFET.
032105
3
SUPERTEX [ Supertex, Inc ]
