HV302 / HV312
Functional Block Diagram
Vint
VDD
Internal
Supply
Regulator
UVLO
and
POR
PWRGD-D
Band Gap
Reference
PWRGD-C
Vbg
UV
LOGIC
Programmable
Timer
PWRGD-B
C
Vbg
OV
C
555 type
Auto-Retry
Timer
PWRGD-A
Vint
Latch High & Sleep
10uA
Vint-1.2V
Transconductor
1:2
Mirror
C
100mV
C
Circuit Breaker
Transconductor
2Vbg
gm
Buffer
Selector
Switch
gm
Selector
Switch
VEE
5k
5k
Clamp Mechanism
SENSE
RAMP
GATE
TB TC TD
Functional Description
Insertion into Hot Backplanes
Telecom, Networking, SAN and Server applications require the
ability to insert and remove circuit cards from systems without
powering down the entire system. All circuit cards have some filter
capacitance on the power rails, which is especially true in circuit
cards or network terminal equipment utilizing distributed power
systems. The insertion can result in high inrush currents that can
cause damage to connector and circuit cards and may result in
unacceptable disturbances on the system backplane power rails.
The HV302 and HV312 are designed to facilitate the insertion of
these circuit cards or connection of terminal equipment by
eliminating these inrush currents and powering up these circuits in
a controlled manner after full connector insertion has been
achieved
Description of Operation
During initial power application, a “normally-on” circuit holds off the
external MOSFET, preventing an input glitch while an integrated
regulator establishes an internal operating voltage of
approximately 10V. Until the proper internal voltage is achieved all
circuits are held reset, the PWRGD flags are inactive and the gate
to source voltage of the external MOSFET is clamped low.
Once the internal under voltage lock out (UVLO) has been
satisfied, the circuit checks the input supply under voltage (UV)
and over voltage (OV) sense circuits to ensure that the input
voltage is within programmed limits. These limits are determined
by the selected values of resistors R1, R2 and R3, which form a
voltage divider.
In
Servo Mode
operation, assuming the UV and OV limits are
satisfied and while continuing to hold the PWRGD flags inactive
and the external MOSFET GATE voltage low, the current source
feeding the RAMP pin is turned on. The external ramp capacitor
connected to it begins to charge, thus starting an initial time delay
determined by the value of the capacitor and the 2Vbg threshold
voltage of the RAMP pin. During this time if the OV or UV limits
are exceeded, an immediate reset occurs and the capacitor
connected to the RAMP pin is discharged.
When the voltage on the RAMP pin exceeds the 2Vbg threshold
voltage, the gate drive circuit begins to apply voltage to the gate of
the external MOSFET, which begins to turn on when its gate
threshold voltage is reached.
The resulting output current
generates a voltage drop on the sense resistor connected between
the SENSE and V
EE
pins, causing a decrease in the available
current charging the capacitor on the RAMP pin. This continuous
feedback mechanism allows the output current to rise inverse
exponentially over a period of a few hundred microseconds to the
sense resistor programmed current limit set point.
When the voltage drop on the sense resistor reaches 50mV the
RAMP pin current is reduced to zero and the voltage on the RAMP
pin will be fixed, indicating that the circuit is in current limit mode.
Depending on the value of the load capacitor and the programmed
current limit, charging may continue for some time, but may not
exceed a nominal 100ms preset time limit. Once the load
capacitor has been charged, the output current will drop, reducing
the voltage on the SENSE pin, which in turn will increase the
RAMP pin current, thus causing the voltage on the capacitor
connected to the RAMP pin to continue rising, thereby providing
yet another programmed delay.
4
Rev. D
04/17/02
Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 Fax: (408) 222-4895 www.supertex.com
SUPERTEX [ Supertex, Inc ]
