HV301/HV311
Functional Block Diagram
UV
C
Regulator & POR
V
IN
Vbg
UVLO
OV
C
Logic
P
U
L
L
H
I
G
H
PWRGD = HV301
PWRGD = HV311
~9.8V
C
Latch High
Sleep
D
I
S
A
B
L
E
V
DD
2V
bg
10µA
1 : 2
mirror
buffer
GATE
RAMP
SENSE
Transconductor
Transconductor
5k
gm
5k
V
EE
Clamp Mechanism
Functional Description
Insertion into Hot Backplanes
Telecom, data networks and some computer applications re-
quire the ability to insert and remove circuit cards from systems
without powering down the entire system. All circuit cards have
some filter capacitance on the power rails, which is especially
true in circuit cards or network terminal equipment utilizing
distributed power systems. The insertion can result in high inrush
currents that can cause damage to connector and circuit cards
and may result in unacceptable disturbances on the system
backplane power rails.
The HV301 and HV311 are designed to facilitate the insertion of
these circuit cards or connection of terminal equipment by
eliminating these inrush currents and powering up these circuits
in a controlled manner after full connector insertion has been
achieved. The HV301 or HV311 is intended to provide this
function on supply rails in the range of
±10
to
±90
Volts.
Description of Operation
During initial power application, a unique proprietary circuit holds
off the external MOSFET, preventing an input glitch while an
internal regulator establishes an internal operating voltage of
approximately 10V. Until the proper internal voltage is achieved
all circuits are held reset, the PWRGD output is inactive and the
gate to source voltage of the external MOSFET is clamped low.
Once the internal under voltage lock out (UVLO) has been
satisfied, the circuit checks the input supply undervoltage (UV)
and overvoltage (OV) sense circuits to ensure that the input
voltage is within programmed limits. These limits are determined
by the selected values of resistors R1, R2 and R3, which form a
voltage divider.
Assuming the above conditions are satisfied and while continu-
ing to hold the PWRGD output inactive and the external MOSFET
GATE voltage low, the current source feeding the RAMP pin is
turned on. The external capacitor connected to it begins to
charge, thus starting an initial time delay determined by the value
of the capacitor. During this time if the OV or UV limits are
exceeded, an immediate reset occurs and the capacitor con-
nected to the RAMP pin is discharged.
When the voltage on the RAMP pin reaches an internally set
threshold voltage, the gate drive circuit begins to turn on the
external MOSFET. In servo mode, once the gate threshold is
reached, the resulting output current generates a voltage drop
on the sense resistor connected between the SENSE and V
EE
pins, causing a decrease in the available current charging the
capacitor on the RAMP pin. This continuous feedback mecha-
nism allows the output current to rise inverse exponentially over
a period of a few hundred microseconds to the sense resistor
programmed current limit set point.
When the voltage drop on the sense resistor reaches 50mV the
RAMP pin current is reduced to zero and the voltage on the
4
SUPERTEX [ Supertex, Inc ]
