HV257
R
SINK
/ R
SOURCE
The V
DD_BYP
,V
DD_BYP
,and V
NN_BYP
pins are internal. high impedance
current. mirror gate nodes, brought out to mantain stable opamp
biasing currents in noisy power supply environments. 0.1uF/25V
bypass capacitors, added from V
PP_BYP
pin to V
PP
, from V
DD_BYP
pin
to V
DD
, and from V
NN_BYP
to V
NN
,will force the high impedance gate
V
PP
B
YP
_V
PP
Cap
0.1uF / 25V
B
YP
_V
PP
B
YP
_V
DD
B
YP
_V
DD
Cap
0.1uF / 25V
V
DD
B
YP
_V
NN
B
YP
_V
NN
Cap
0.1uF / 25V
V
NN
Current limit
Set by R
SINK
Current limit
nodes to follow fluctuation of power lines. The expected voltages
at the V
DD_BYP
, and V
NN_BYP
pins are typically 1.5 volts from their
respectful power supply. The expected voltage at V
PP_BYP
is typically
3V below V
PP
.
Set by R
SOURCE
To internal biasing
HV
OUT
0
HV
OUT
31
HVOpamp
HVOpamp
Ground Isolation (A
GND
/D
GND
Isolation)
It is important that the A
GND
pin is connected to a clean ground.
The hold capacitors are internally connected to the A
GND
, and any
ground noise will directly couple to the high voltage outputs (with
a gain of 72). The analog and digital ground traces on the PCB
should be physically separated to reduce digital switching noise
degrading the signal to noise performance.
D
GND
C2
DV
DD
DAC
C3
DV
NN
EN, A
0
-A
4
External bypass caps:
C1 = 0.1µF / 500V
C2, C3, C4, C5 = 0.1µF / 25V
V
SIG
Sample
switch
LVOpamp
HVOpamp
HV
OUT
C_hold
10pF
AV
NN
C4
C5
C6
A
GND
1 (pins 89, 43)
Single star GND
AV
DD
C_comp
1R
V
PP
71R
C1
C_comp
A
GND
2 (pin 39)
6
SUPERTEX [ Supertex, Inc ]
