HV111
Programming UVLO
GND
V
PP
V
PP
V
PP
R1
2.4MΩ
1mA
R
1
Enable
PWRGD
UVLO
Q
1
R2
116k
1.2V
V
NN
V
NN
-48V
Internal to
HV111
DRAIN
Figure 3
−
Programming UVLO
The UVLO/ENABLE pin makes it easy to override the
internal 26V nominal under voltage. The 26V nominal setting
is produced by a resistor divider of 2.4MΩ and 116k. These
are 20% resistors, however, 1% accurate relative to one
another. To override there are two options. The first is to
simply use a much lower impedance divider, for example
200k, and largely ignore the internal divider. Alternatively,
the internal impedance may be taken into a account in the
network and the UVLO calculated as:
V
PP
*(R2||116k) / (R1||2.4MΩ+R2||116k)
Keep in mind, however, that the 30% variation on the
internal resistors will reduce the accuracy of the UVLO set
point using this approach.
Note that the UVLO/ENABLE pin may also be used as an
enable with a nominal 1.20V trip point and 10% of
hysteresis.
Figure 4
−
PWRGD Active High
The above circuit works as follows for ACTIVE HIGH
operation. If the PWRGD is low, then the current sourced by
the pullup is pulled to V
NN
and the BJT, Q1, is starved for
base drive current and remains off. The reverse Vbe voltage
is protected by the series diode, D1. If PWRGD is open,
then the current has no alternative but to flow into the base
and thus connects the DC/DC ENABLE pin to the DC/DC
ground reference (DRAIN pin of the HV111). As the clamp is
inverting, therefore proper ACTIVE high polarity is
established.
The resistor, R1, should be sized as V
PP
/1mA to ensure that
the maximum PWRGD transistor current is not exceeded
(remember to use the maximum possible V
PP
your circuit will
see rather than the nominal value of V
PP
).
Further, Q1 must be rated for operation to maximum
expected V
PP
and have a beta large enough that the
minimum V
PP
min/V
PP
max*1mA*β
min
> Ipullupmax of the
DC/DC converter (or external resistor if used).
optional
GND
PWRGD Active High or Active Low
(for DC/DC HV Interface / Enable)
The PWRGD pin is an open drain active low MOSFET which
is enabled when the gate voltage on the internal power
MOSFET reaches its full on voltage. The PWRGD output is
nominally ACTIVE LOW, however, the simple circuit shown
(Figure 4) can convert it to active high operation.
-48V
BAT
DC/DC
V
PP
DC/DC
V
O
PWRGD
UVLO/
Enable
ENABLE
GND
V
NN
DRAIN
HV111
Figure 5
−
PWRGD Enable
Also shown in Figure 5 is decoupling capacitor is not strictly
required, a fast dv/dt on PWRGD bar can result in coupling
that can glitch the UVLO pin. This decoupling capacitor
ensures that glitches will be eliminated.
4
SUPERTEX [ Supertex, Inc ]
