SMS1242
Symbol
fSCL
Parameter
SCL clock frequency
Clock low period
Conditions
Min.
0
Max.
Units
100
kHz
tLOW
tHIGH
tBUF
4.7
4.0
4.7
4.7
4.0
4.7
0.3
0.3
µs
Clock high period
µs
Bus free time
Before new transmission
µs
tSU:STA
tHD:STA
tSU:STO
tAA
Start condition setup time
Start condition hold time
Stop condition setup time
Clock edge to valid output
Data Out hold time
SCL and SDA rise time
SCL and SDA fall time
Data In setup time
µs
µs
µs
SCL low to valid SDA (cycle n)
3.5
µs
tDH
SCL low (cycle n+1) to SDA change
µs
tR
1000
300
ns
tF
ns
tSU:DAT
tHD:DAT
TI
250
0
ns
Data In hold time
ns
ns
Noise filter SCL and SDA
Write cycle time
Noise suppresion
100
5
tWR
ms
2038 Table01 2.0
t
t
LOW
HIGH
t
t
R
F
SCL
t
t
t
t
SU:STO
t
HD:DAT
SU:SDA
SU:DAT
HD:SDA
t
BUF
SDA In
t
t
AA
DH
SDA Out
2038 Fig07 2.0
Figure 7. Memory Timing
SUMMIT MICROELECTRONICS, Inc.
2038 2.0 6/8/00
6
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
