SMS1242
DEVICE OPERATION
below V
, a brownout condition that interrupts a previ-
The SMS1242 provides a precision reset function for a
microcontroller or microprocessor during power-up,
power-down and brown-out conditions. The device will
monitor two independent voltage supplies and will gener-
ate a reset condition when either supply is invalid. It is
configured with two outputs, both driven by the same
conditions. They are open drain and will track each other
but the outputs are not internally tied together.
RST
ouslyinitiatedresetpulsecausesanadditionalresetdelay
from the time the V passes back through V
.
RST
CC
During power down conditions, once V
drops below
CC
V
, RESET1# and RESET2# are guaranteed to be
RST
asserted for V ≥ 1V.
CC
VSENSE MONITOR
Because RESET1# and RESET2# are essentially open
drain outputs (RESET1# has a weak internal pullup,
RESET2#doesnot)theycanbeindependentlydrivenlow
by external signals. This can be very useful in a dual
processor system or in a combined processor/ASIC sys-
tem where, either for system operation or system test, the
processors or ASICs must be independently held in reset
without resetting the other portion of the system.
(Assume V
is >V
) The SMS1242 continuously
RST
CC
monitors the VSENSE input. The RESET1# and RE-
SET2# outputs will be driven low so long as V is <
SENSE
an internal timer
SNS
VSNS. As V
passes through V
SENSE
is started to continue driving the outputs for an additional
150ms (nom.).
If a power-fail condition occurs (V
falls below V
)
SENSE
SNS
RESET1# and RESET2# will be asserted. They will re-
main active so long as V is below V . Because
SUPPLY MONITOR
SENSE
SNS
the internal timer will be continuously reset so long as
is below V , a brownout condition that inter-
(AssumeV
> V
)Duringpower-uptheSMS1242
SENSE
SNS
V
SENSE
SNS
monitors the supply voltage. The RESET1# and RE-
SET2# outputs are guaranteed to be driven low once V
reaches 1V. As V
rupts a previously initiated reset pulse causes an addi-
tional reset delay from the time V becomes greater
CC
SENSE
rises RESET1# and RESET2#
CC
than V
.
SNS
remainasserteduntilV reachestheV
threshold. As
RST
CC
V
CC
passes through V
an internal timer is started to
RST
MANUAL RESET
continue driving the outputs for an additional 150ms
(nominal).
ThemanualresetinputallowsRESET1#andRESET2#to
be activated by a pushbutton switch. The switch is
If a power-fail or brown-out condition occurs (V < V
)
RST
CC
effectively debounced by the 100ms minimum t
(RE-
RESET1# and RESET2# will be asserted. They will
remain active so long as V is below V . Because the
RST
SET pulse width). MR# can also be driven by an external
logic input that meets the 50ns minimum pulse width
required.
CC
RST
internal timer will be continuously reset so long as V is
CC
Unregulated
+12V DC
3.3V Out
DC to DC
Converter
3.3V
MCU
VCC
VCC
RESET1#
VSENSE
MCU #1
MR#
RESET1#
SMS1242
SMS1242
RESET2#
Test Point #1
Test Point #2
VSENSE
Low Voltage
High Speed
ASIC
MR#
ASIC or MCU #2
RESET2#
1.8V
2038 ILL8.0
2038 ILL7.0
Figure 5. Typical Multi-MCU Implementation
Figure 6. Typical Dual Voltage Implementation
2038 2.0 6/8/00
SUMMIT MICROELECTRONICS, Inc.
5
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
