SMM151/152
Preliminary Datasheet
PIN DESCRIPTIONS
Pin
Pin
Pin Name
Pin Description
Number
Type
28
1
I/O
SDA
SCL
A2
A1
A0
I2C Bi-directional data line
I2C clock input.
The address pins are biased either to VDD, GND or left floating. This allows
for a total of 21 distinct device addresses. When communicating with the
SMM151/2 over the 2-wire bus these pins provide a mechanism for
assigning a unique bus address.
I
2
I
I
4
6
I
I/O
NC
GPIO0,1,2,3 SMM152: General purpose inputs/outputs.
3, 9, 22, 27
8
NC
SMM151: No Connect.
Programmable Write Protect active high/low input. When asserted, writes to
the configuration registers and general purpose EE are not allowed. The
WP input is internally tied to VDD with a 50KΩ resistor.
I
WP
10, 13
20
CAP
O
CAPM+, -
TRIM
External capacitor inputs used to filter the VM+/VM- inputs, 0.22µF.
Output voltage used to control and/or margin converter voltages. Connect to
the converter trim input.
Voltage monitor input. Connect to the DC-DC converter positive sense line
or it’s +Vout pin.
14
15
18
17
26
I
VM+
VM-
Voltage monitor input. Connect to the DC-DC converter negative sense line
or it’s -Vout pin.
I
Current monitor input + side. Connect to the input supply side of the current
sense resistor.
I
I
CS+
CS-
Current monitor input - side. Connect to the load side of the current sense
resistor.
Internal reference voltage of 1.25V. Connect to GND through a 0.1uF
PWR
VREF
capacitor to improve noise immunity.
16
21
23
O
CAPC
VDD
VDD_CAP
External capacitor input used to filter the CS+/CS- input. Typical value: 1uF.
Power supply of the part.
PWR
PWR
External capacitor input used to filter the internal VDD supply rail.
Ground of the part. The SMM151/2 ground pin should be connected to the
ground of the device under control or to a star point ground. PCB layout
should take into consideration ground drops.
7
GND
GND
Margin up command input. Asserted high. The MUP input is internally tied to
VDD with a 50KΩ resistor.
24
25
I
I
MUP
MDN
Margin down command input. Asserted high. The MDN input is internally
tied to VDD with a 50KΩ resistor.
COMP1 and COMP2 are high impedance inputs, each connected internally
to a comparator and compared against the internally programmable VREF
voltage. Each comparator can be independently programmed to monitor for
UV or OV. The monitor level is set externally with a resistive voltage
divider.
When either of the COMP1 or COMP2 inputs are in fault the open-drain
FAULT# output will be pulled low. A configuration option exists to disable
the FAULT# output while the device is margining.
19
12
I
I
COMP1
COMP2
11
O
FAULT#
Summit Microelectronics, Inc
2131 2.148/15/2008
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
