SMM151/152
Preliminary Datasheet
INTERNAL BLOCK DIAGRAM
VREF
READY
FAULT#
VDD
VDD_CAP
GND
COMP1
COMP2
OV/UV
OV/UV
VREF
0.5V/1.25V
Glitch
Filter
Output
Control
VREF = 1.25V
50kΩ
Up/Dn
MUP
TRIM
Digital
Margin
Control
8-bit DAC
Comparator
Target
Logic
MDN
Halt
SW1
50kΩ
Clock
MUX
A0
A1
SW2
10Bit
ADC
I2C
A2
SCL
SDA
Interface
CAPM+
CAPM-
WP
25kΩ
25kΩ
VM+
VM-
GPIO0
GPIO1
GPIO2
GPIO3
EE
Control
Logic
Configuration
Registers
& Memory
CAPC
CS+
SMM152
250kΩ
DIFF
AMP
CS-
Figure 2 – SMM151 and SMM152 Controller Internal Block Diagram.
PACKAGE AND PIN DESCRIPTION
28-Pad 5x5 QFN
Top View
() applies on SMM152
Pin 1
28 27 26 25 24 23 22
1
21
20
19
SCL
VDD
2
3
A2
(GPIO0)
A1
TRIM
COMP1
CS+
SMM150
4
5
6
7
GND
18
17
16
15
READY
A0
CS-
CAPC
VM-
GND
13
14
8
9
10 11
12
Summit Microelectronics, Inc
2131 2.138/15/2008
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
