SMM150
Preliminary Information
INTERNAL BLOCK DIAGRAM
FAULT#
READY
VDD
VREF =
COMP1
1.25V or 0.5V
OV/UV
OV/UV
VDD_CAP
GND
VREF
VREF
Glitch
Filter
Output
Control
COMP2
TRIM
50kΩ
Up/Dn
MUP
MDN
Digital
Margin
Control
8-bit DAC
Comparator
Target
Logic
Halt
SW1
50kΩ
Clock
MUX
A0
A1
10Bit
ADC
I2C
A2
SCL
SDA
VM
Interface
SW2
WP
EE
Configuration
Registers
& Memory
CAPM
Figure 2 – SMM150 Controller Internal Block Diagram.
PACKAGE AND PIN CONFIGURATION
28 Pad QFN
20 Ball Ultra CSPTM
Top View
Bottom View
Pin 1
SCL
MDN VDD_CAP VDD
Pin 1
A1
A2
A2
SDA
A3
TRIM
B3
A4
COMP1
B4
NC
23
28 27 26 25 24
22
1
21
20
19
SCL
A2
VDD
TRIM
COMP1
NC
B1
A1
B2
READY
2
3
GND
NC
MUP
SMM150
4
5
6
7
or
18
17
16
15
A1
C1
A0
C2
WP
C3
FAULT#
D3
C4
NC
READY
A0
NC
NC
NC
GND
NC
D1
GND
E1
D2
CAP_M
D4
VM
13
14
9
10 11
8
12
COMP2
E2
E3
E4
Summit Microelectronics, Inc
2075 2.6 05/13/05
3
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
