SMM105
Preliminary Information
INTERNAL BLOCK DIAGRAM
VREF_CNTL
V
R EF
MUX
R EADY
FA ULT#
CO MP1
O V/UV
V+
V-
O utput
Control
CO MP2
Trim
Drive
TRIM
TRIM _CAP
O V/UV
S TA RT
W P#
A0
A1
A2
SD A
SCL
I
2
C Serial
Interface
12V IN
3.6/5V
Regulator
Supply
Arbitration
Input Voltage
Sensing and
Signal
Conditioning
EE
Configuration
Registers
& M em ory
VM
V DD
VDD_C AP
Figure 3 – SMM105 Controller Internal Block Diagram.
PACKAGE AND PIN CONFIGURATION
28 Pin QFN
Top View
25 Ball
Ultra
CSP
TM
Bottom View
Pin 1
SDA
NC
NC
NC
NC
VDD_CAP
12VIN
Pin 1
SCL
21
20
19
18
17
16
15
A2
SDA VDD_CAP 12VIN
28 27 26 25 24 23 22
SCL
A2
START
A1
READY
A0
GND
1
2
3
4
5
6
7
8
9 10 11 12 13 14
SMM105
VDD
TRIM
COMP1
TRIM_CAP
NC
NC
NC
A1
START
A2
A1
A3
NC
A4
VDD
A5
TRIM
B1
READY
B2
A0
B3
NC
B4
C4
NC
B5
C5
NC
COMP1 TRIM_CAP
C1
D1
E1
C2
D2
E2
C3
D3
E3
GND VREF_CNTL FAULT#
D4
VM
D5
NC
WP#
VREF_CNTL
FILT_CAP
FAULT#
COMP2
NC
VM
WP# FILT_CAP COMP2
E4
E5
Summit Microelectronics, Inc
2068 1.8 09/20/05
3
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
