SMH4811A
Preliminary
charging the filter capacitance (normally required at the Current Regulation
input of the DC/DC controller) too quickly may generate
The current regulation mode is an optional feature that
provides a means to regulate current through the MOS-
FET for a programmable period of time. If enabled the
device will start the internal timer when the voltage at
CBSENSE exceeds 50mV. Also, it attempts to limit the
voltage at CBSENSE to 60mV by regulating the VGATE
output. The circuit breaker will trip if the over-current
condition remains after the time-out. However, if CB-
SENSE drops below 50mV before the timer ends, the
timer is reset and VGATE resumes normal operation. If
the Quick-Trip level is exceeded then the device will
bypass the current regulation timer and shut down imme-
diately. The Current Regulation feature is disabled in the
default configuration.
very high current. The VGATE output of the SMH4811A
is current limited to IVGATE, allowing the slew rate to be
easily modified using external passive components. The
slew rate may be found by dividing IVGATE by the gate-to-
draincapacitanceplacedontheexternalFET. Acomplete
design example is given in the Applications Section.
Load Control — Sequencing the Secondary Sup-
plies
Once power has been ramped to the DC/DC controllers,
two conditions must be met before the PG# output can be
enabled: the Drain Sense voltage must be below 2.5V,
and the VGATE voltage must be greater than VDD –VGT.
The Drain Sense input helps ensure that the power MOS-
FET is not absorbing too much steady state power from Non-Volatile Fault Latch
operating at a high VDS. This sensor remains active at all
TheSMH4811Aalsoprovidesanoptionalnonvolatilefault
times (except during the current regulation period). The
VGATE sensor makes sure that the power MOSFET is
operatingwellintoitssaturationregionbeforeallowingthe
load to be switched on. Once VGATE reaches VDD –VGT
this sensor is latched.
latch (NVFL) circuit breaker feature. The nonvolatile fault
latch essentially provides a programmable fuse on the
circuit breaker. When enabled the nonvolatile fault latch
will be set whenever the circuit breaker trips. Once set, it
cannot be reset by cycling power.
Once the external MOSFET is properly switched on the
PG# output may be enabled (if ENPG is high). The PG#
output has a 12V withstand capability, so high voltages
must not be connected to this pin. A bipolar transistor or
opto-isolatorcanbeusedtoboostthewithstandvoltageto
that of the host supply.
NOTE: THE DEVICE REMAINS PERMANENTLY DISABLED
UNTIL IT IS REPROGRAMMED AT THE FACTORY.
As long as the NVFL is set the FAULT# output will be
driven active. The Non-Volatile Fault Latch feature is
disabled in the default configuration.
Resetting FAULT#
Circuit Breaker Operation
When the circuit breaker trips the VGATE output is turned
off and FAULT# is driven low. In the default condition the
breaker resets automatically after a time of tCYC. In the
latchedconditioncyclingpowertotheboardortogglingthe
EN/TS input will also reset the circuit breaker. If the over
current condition still exists after the MOSFET switches
back on, the circuit breaker will re-trip.
The SMH4811A provides a number of circuit breaker
functions to protect against over current conditions. A
sustained over-current event could damage the host sup-
ply and/or the load circuitry. The board’s load current
passes through a series resistor (RS) connected between
theMOSFETsource(whichistiedtoCBSENSE)andVSS.
The breaker trips whenever the voltage drop across RS is
greater than 50mV for more than tCBD (a factory program-
mable filter delay ranging from 10µs to 500µs).
Quick-TripTM Circuit Breaker
Additionally,theSMH4811AprovidesaQuick-Tripfeature
that will cause the circuit breaker to trip immediately if the
voltage drop across RS exceeds VQCB. The Quick-Trip
level may be factory set to 60mV, 100mV (default),
200mV, or the feature may be disabled.
SUMMIT MICROELECTRONICS, Inc.
2044 6.1 2/8/01
8
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
