SMH4814
Preliminary Information
CONFIGURATION REGISTERS (CONTINUED)
Register R12 – Write protect and Write lockout, feedback pin control settings.
Register R12
D7
D6
D5
D4
D3
D2
D1
D0
Action
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Not Used
-
-
-
-
0
1
Set WP on Power-up (0-don’t set WP; 1-set WP)
Set WP on Power-up (0-don’t set WP; 1-set WP)
Write Lockout = allows writes to the config or
memory)
-
-
-
0
-
-
-
-
Write Lockout = prevents writes to the config or
-
-
-
1
-
-
-
-
memory
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
1
-
-
-
-
-
0
1
-
-
-
-
-
-
-
-
-
FBD enable = disable pin input
FBD enable = enable pin input
FBC enable = disable pin input
FBC enable = enable pin input
FBB enable = disable pin input
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
-
0
1
FBB enable = enable pin input
FBA enable = disable pin input
FBA enable = enable pin input
-
-
Fault/Status Registers
The following tables describe the 24 bits within the Fault/Status Registers. When Bit 7 of Register 0x04 (Slave
address 1001) is low, then the data within these registers represents the real-time state of the part. When Bit 7 is
high, then these registers represent data that was latched at the time that the Fault occurred. There are three
Status/Fault Registers, accessed at slave address 1001 with address bit A8 set low, at word address 0x02-0x04.
Register 0x02 Description
Bit #
Regsiter 0x03 Description
Bit #
Regsiter 0x04
Description
Bit #
7
PUPD
7
GATEB OFF
7
Fault Register is
Latched
6
5
PUPC
PUPB
6
5
GATEA OFF
Over-Current
Fault
6
5
Write Protect Status
reserved
4
3
2
1
0
PUPA
FBD
FBC
FBB
FBA
4
3
2
1
0
FET is ON
ENTS Fault
PD Fault
4
3
2
1
0
reserved
FB Fault
reserved
reserved
reserved
OV Fault
UV Fault
Summit Microelectronics, Inc
2080 2.0 07/21/05
40
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
