SMH4814
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Active FET Gate Control
The duration of each time slot is programmable to one
of 16 values ranging from 250µs to 768ms. When
Time Slot 0 times out, then the PUP outputs assigned
to that time slot are enabled. Time Slot 1 begins when
the affiliated feedback pins are pulled high. For
example, if PUPA and PUPC are assigned to Time Slot
0, then Time Slot 1 begins only after PUPA and PUPC
are enabled, and FBA and FBC are pulled high. If there
are no PUP outputs assigned to a given time slot, then
the next time slot commences as soon as the current
time slot times out. This process continues until all
four time slots have timed out and all feedback pins
have been pulled high. At this point, the brick
sequencing is complete. The device also sequences
down in the same manner (Figure 6).
Throughout the power-up process, the Active-ORing
FET’s are kept off. Current flows by means of the
body diodes of those MOSFET devices. Once all of
the PUP outputs of the SMH4814 have been enabled,
one of the Active-ORing FET’s may now be enabled.
Initially, the feed with the lowest negative potential is
the one selected to power the load. To determine the
lowest supply, an on-board comparator determines
which input (FEEDA or FEEDB) is lower. Since the
actual feeds may both be below VSS due to the drop
across the body diodes, the FEEDA and FEEDB inputs
are level shifted up by delivering a current across a
dropper resistor (typically 100k). The FEED output
current is programmable from 10µA-25µA, using
R07[7:4]. The VGATE output corresponding to the
lowest FEED input is driven to V12.
The PUPx outputs have a 12V withstand capability, so
high voltages must not be connected to these pins.
Bipolar transistors or opto-isolators can be used to
boost the withstand voltage to that of the host supply
The FEEDA and FEEDB inputs are continually
monitored for the lowest input level so that the
corresponding power feed will be the one used to
energize the load. However, once one of the Active
FET gates has been driven high, the level shifting
currents being delivered out of FEEDA and FEEDB
may be skewed to offer some degree of hysteresis.
The current driven out of the non-selected feed is
increased by anywhere from 0 to 15µA, as determined
by R07[3:0]. The effect of the increased current is to
make the non-selected feed appear to have an even
higher potential, and thereby offering a level of
hysteresis. The hysteresis will help to reduce the
amount of unnecessary switching between feeds in
cases where the two potentials are very close together
or where there is excessive noise on the feeds.
FB Inputs
The FBx pins are designed to receive feedback from
the secondary side of the bricks and are used to
indicate that an enabled brick has powered up
properly. The previous section described the PUPX
output enabling sequence when the SMH4814
receives the expected feedback from the secondary
side. This section describes what happens when a
FBX pin stays low or goes low unexpectedly.
As described above, when a given time slot times out,
the appropriate PUP output is enabled. The next time
slot will not commence until the associated FB pin is
pulled high. The sequence termination timer (STT) is
used to protect against a stalled Power-on sequence.
This timer commences when the PUPx outputs within
a given time slot are enabled, and it continues running
until either all associated FBx inputs go high or the
sequence termination timer times out (tSTT). If the STT
times out before the appropriate FB inputs go high the
device will power down the PUP and VGATE outputs.
This control mechanism allows supplies that have
dependencies based on the other voltages in the
system to be cascaded properly.
When it is determined that the selected feed is no
longer the most appropriate one to power the load, the
corresponding VGATE output is immediately switched
off via
a
powerful pull-down device.
The
complementary output is then enabled using a current
limited pull-up. The amount of current is selectable
from 10µA –200µA using R05[5:4].
The status registers contain bits that indicate the
sequence has been terminated and in which sequence
position the timer timed out.
Summit Microelectronics, Inc
2080 2.0 07/21/05
16
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
