SMH4814
Preliminary Information
APPLICATIONS INFORMATION
CHASSIS
CARD
100k
RD
General Purpose EEPROM
The SMH4814 has 256 bytes of general-purpose
EEPROM memory available to the user. These 2k-
bits of EEPROM are accessible via the I2C interface at
slave address 1010 or 1011, beginning at word
address 0 (0x000) and ending at word address 255
(0x0FF). Refer to the I2C 2-Wire Serial Interface
section for more information.
-48V Ret
PD1
Configuration Registers
SMH4814
PD0
-48V A
-48V B
There are also 20 user-programmable, non-volatile
configuration registers on the SMH4814. The
configuration registers are accessible via the IIC
interface at the same slave address as the general
purpose EEPROM, beginning at word address 256
(0x100) and ending at address 271 (0x113). These
locations will be referred to throughout this document
as registers R00 through R13. Individual bits or
ranges of bits will be further denoted with square
brackets. For example, R00[3:0] refers to Register
0x100, bits 3 through 0. R0D[6,2] refers to Register
0x10D, bits 6 and 2. The configuration registers are
responsible for setting all of the programmable
parameters described within this document. Refer to
the Configuration Register Tables for more detailed
information about all the register settings.
100k
Short Pins
Figure 8 - PD1 and PD0 Inputs, Physical Offset
Two shorter pins, arranged at opposite ends of the
connector, force the card to be fully seated before both
pin detects are enabled. It is important to use limiting
resistors (typically 100k to 1M) in series with the PD
inputs to avoid damaging them. An internal shunt
prevents the voltage on those pins from reaching
unsafe levels.
Pin Detection
The PD inputs may be disabled using R0F[2];
however, even if the Pin Detect inputs are disabled or
tied directly to 5V, the device must still wait a pin
detect delay period before starting up. The pin detect
delay (tPDD) timing parameter is controlled by bits
R00[3:0]. Refer to Register R00 and R0F for detailed
programming information.
There are several enabling inputs that allow the host
to control the SMH4814. The Pin Detect signals (PD1
and PD0) are two active high enables that are
generally used to indicate that the add-in circuit card is
properly seated. These inputs must be held high for a
pin-detect delay period of tPDD before a power-up
sequence may be initiated. This is typically done by
clamping the inputs to 5v through the implementation
of an ejector switch, or alternatively through the use of
staggered pins at the card-cage interface.
EN/TS Input
The EN/TS input provides an active high comparator
input that may be used as a master enable or
temperature sense input. This input signal must
exceed 2.5V to enable the FET turn-on sequence. If
EN/TS drops below the 2.5V sense level, the device
may be configured to set the FAULT# output or not,
and initiates either a Forced Shutdown or Power Down
sequence. These options are set using R0D[6,2].
Summit Microelectronics, Inc
2080 2.0 07/21/05
13
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
