SMH4814
Preliminary Information
I2C 2-WIRE SERIAL INTERFACE
Acknowledge
Programming Information
I2C Bus Interface
Data is always transferred in bytes. Acknowledge
(ACK) is used to indicate a successful data transfer.
The transmitting device releases the bus after
transmitting eight bits. During the ninth clock cycle the
Receiver pulls the SDA line low to acknowledge that it
received the eight bits of data. This is shown by the
ACK callout in Figure 17.
When the last byte has been transferred to the Master
during a read of the SMH4814, the Master leaves SDA
high for a Not Acknowledge (NACK) cycle. This
causes the SMH4814 part to stop sending data, and
the Master issues a Stop on the clock pulse following
the NACK.
The I2C bus interface is a standard two-wire serial
protocol that allows communication between
integrated circuits. The data line (SDA) is a bi-
directional I/O; the clock line (SCL) runs at speeds of
up to 400kHz. The SDA line must be connected to a
positive logic supply through a pull-up resistor located
on the bus.
Start and Stop Conditions
Both the SDA and SCL pins remain high when the bus
is not busy. Data transfers between devices may be
initiated with a Start condition. A high-to-low transition
of the SDA input while the SCL pin is high is defined
as a Start condition. A low-to-high transition SDA while
SCL is high is defined as a Stop condition. Figure 16
shows a timing diagram of the start and stop
conditions.
Figure 17 shows the Acknowledge timing.
Figure 17 - Acknowledge Timing
Read and Write
Figure 16 - Start and Stop Conditions
Master/Slave Protocol
The first byte from a Master is always made up of a 7-
bit Slave address and the Read/Write (R/W) bit. The
R/W bit tells the Slave whether the Master is reading
data from the bus or writing data to the bus (1 = Read,
0 = Write). The first four of the seven address bits are
called the Device Type Identifier (DTI). In the case of
the SMH4814, the next two bits are Bus Address
values , used to distinguish multiple devices on a
common bus. The seventh bit of the slave address
represents the ninth bit of the word address. The
SMH4814 issues an Acknowledge after recognizing a
Start condition and its DTI. Figure 18 shows an
The master/slave protocol defines any device that
sends data onto the bus as a transmitter, and any
device that receives data as a receiver. The device
controlling data transmission is called the Master, and
the controlled device is called the Slave. In all cases
the SMH4814 is referred to as a Slave device since it
never initiates any data transfers. One data bit is
transferred during each clock pulse. The data on the
SDA line must remain stable during clock high time,
because a change on the data line while SCL is high is
interpreted as either a Start or a Stop condition.
example of
transmission.
a
typical master address byte
Summit Microelectronics, Inc
2080 2.0 07/21/05
24
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
