SMH4812
Preliminary
Under-Voltage Hysteresis
timer allows the SMH4812 to ignore the state of the FS#
inputuntilthetimerperiodexpires. TheFS#inputmustbe
driven high by the end of this timer period. A low level on
this input will cause a Fault condition, driving FAULT# low
and shutting off the VGATE and PG# outputs.
The Under-Voltage comparator input may be configured
with a programmable level of hysteresis. The compare
level may be set in steps (up to 15) of 62.5mV below 2.5V.
The default under-voltage hysteresis level is set to
62.5mV.
Thepurposeoftheholdofftimeristoallowenoughtimefor
devicesonthesecondarysideoftheDC/DCcontrollersto
power up and stabilize. This unique feature of the
SMH4812 allows supervisory circuits such as an SMS44
tocontroltheshutdownoftheprimarysidesoftstartcircuit,
even though the secondary side initially has no power.
Soft Start Slew Rate Control
Once all of the preconditions for powering up the DC/DC
controllers have been met, the SMH4812 provides a
means to soft start the external power FET. It is important
to limit in-rush current to prevent damage to the add-in
cardordisruptionstothehostpowersupply. Forexample,
charging the filter capacitance (normally required at the
input of the DC/DC controllers) too quickly may generate
very high current. The VGATE output of the SMH4812 is
currentlimitedtoIVGATE,allowingtheslewratetobeeasily
modified using external passive components. The slew
rate may be found by dividing IVGATE by the gate-to-drain
capacitance placed on the external FET. A complete
design example is given in the Applications Section.
The FS# input can be programmed to act as a second
ENPG input controlling the PG# output.
Circuit Breaker Operation
The SMH4812 provides a number of circuit breaker func-
tions to protect against over current conditions. A sus-
tained over-current event could damage the host supply
and/or the load circuitry. The board’s load current passes
through a series resistor (RS) connected between the
MOSFET source (which is tied to CBSENSE) and VSS.
The breaker trips whenever the voltage drop across RS is
greater than 50mV for more than tCBD (a programmable
filter delay ranging from 10µs to 500µs).
Load Control — Sequencing the Secondary Sup-
plies
Once power has been ramped to the DC/DC controllers,
two conditions must be met before the PG# output can be
enabled: the Drain Sense voltage must be below 2.5V,
and the VGATE voltage must be greater than VDD – VGT.
The Drain Sense input helps ensure that the power MOS-
FET is not absorbing too much steady state power from
operating at a high VDS. This sensor remains active at all
times (except during the current regulation period). The
VGATE sensor makes sure that the power MOSFET is
operatingwellintoitssaturationregionbeforeallowingthe
loads to be switched on. Once VGATE reaches VDD – VGT
this sensor is latched.
Quick-TripTM Circuit Breaker
Additionally, the SMH4812 provides a Quick-Trip feature
that will cause the circuit breaker to trip immediately if the
voltage drop across RS exceeds VQCB. The Quick-Trip
levelmaybesetto60mV, 100mV(default), 200mV, orthe
feature may be disabled.
<T
CBD
When the external MOSFET is properly switched on the
PG#outputmaybeenabled(ifENPGishigh). OutputPG#
is activated after a tPGD delay. The delay time is program-
mable from 50µs to 160ms.
V
QCB
50mV
CBSENSE
The PG# output has a 12V withstand capability, so high
voltages must not be connected to this pin. A bipolar
transistor or an opto-isolator can be used to boost the
withstand voltage to that of the host supply. See Figure 9
for connections.
T
FSTSHTDN
VGATE
Forced Shutdown — Secondary Feedback
2055 Fig04
The Forced Shutdown signal (FS#) is an active low input
that provides a method of receiving feedback from the
secondarysideoftheDC/DCcontrollers. Abuilt-inholdoff
Figure 4. Circuit Breaker Quick Trip Response
SUMMIT MICROELECTRONICS, Inc.
2055 4.0 12/22/00
9
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
