SMH4042A
POWERSWITCHINGOPTIONS
rightexamplebothVGATEoutputsarebeingusedsothat
The figures below illustrate four possible methods for
wiringtheSMH4042A. Intheupperleftexamplebothpower the 3.3V slew lags the 5V slew. The two bottom circuits
FETs are connected to a single VGATE output. This illustrate the wiring for single power supply boards. Note
should be used when the design requires the backend how the VSEL pin is biased differently for the two
voltages to be powered-up simultaneously. In the upper applications.
VCC
VCC
CBI_5
CBI_5
10Ω
10Ω
10Ω
47nF
VGATE5
VGATE5
5V 5ꢀ
5A max
5V 5ꢀ
5A max
CARD_5V_MON
CARD_5V_MON
VSEL
VSEL
3.3V 0.3V
7.6A max
3.3V 0.3V
7.6A max
CARD_3V_MON
VGATE3
CARD_3V_MON
VGATE3
10Ω
47nF
47nF
CBI_3
CBI_3
0.0065Ω
HST_3V_MON
0.0065Ω
HST_3V_MON
Dual Voltage, Single Slew Rate Implementation
Dual Voltage, Dual Slew Rate Implementation
VCC
VCC
CBI_5
CBI_5
10Ω
VGATE5
VGATE5
47nF
5V 5ꢀ
5A max
CARD_5V_MON
VSEL
CARD_5V_MON
VSEL
3.3V 0.3V
7.6A max
CARD_3V_MON
VGATE3
CARD_3V_MON
VGATE3
10Ω
47nF
CBI_3
CBI_3
0.0065Ω
HST_3V_MON
HST_3V_MON
Single 5V Implementation
Single 3.3V Implementation
Figure 14. Four Power Switching Implementations
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
18
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
