SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION
either the PWREN pin or by the contents of the enable
register.
When enabling a channel from the enable register, the
register contents default state must be set so that the
output will be enabled or disabled following a POR
(power on reset). The default state is programmable.
DEVICE OPERATION
POWER SUPPLY
There are five supply input pins on the SMB113A/B
and SMB117/A: four HVSUP pins and the VBATT pin.
Each supply must be powered from an input voltage
between 2.7-6.0 volts.
The HVSUP1 though HVSUP4 are used to power the
HSDRV (PMOS driver) and LSDRV (NMOS driver)
outputs. The rail-to-rail swing on the HSDRV and
LSDRV pins is equal to the associated HVSUP supply
voltage.
The VBATT pin is internally regulated to 2.5V. This
2.5V supply is then filtered on the VDD_CAP pin and
used to power all internal circuitry. The VBATT pin is
monitored by an Under-Voltage Lockout (UVLO)
circuit, which prevents the device from turning on
when the voltage at this node is less than the UVLO
threshold.
CASCADE SEQUENCING
Each channel on the SMB113A/B and SMB117/A may
be placed in any one of 4 unique sequence positions,
as assigned by the configurable non-volatile register
contents. The SMB113A/B and SMB117/A navigate
between each sequence position using a feedback-
based
cascade-sequencing
circuit.
Cascade
sequencing is the process in which each channel is
continually compared against programmable
a
reference voltage until the voltage on the monitored
channel exceeds the reference voltage, at which point
an internal sequence position counter is incremented
and the next sequence position is entered. In the
event that a channels enable input is not asserted
when the channel is to be sequenced on, that
sequence position will be skipped and the channel in
the next sequence position will be enabled.
OUTPUT VOLTAGE
All output voltages on the SMB113A/B and SMB117/A
can be set via the non-volatile configuration registers.
Each of the four step-down output voltages on the
SMB113A/B and SMB117/A can be adjusted for 100%
duty cycle or 0% duty cycle operation.
When 100% duty cycle mode is selected, the output
voltage can be set up to the input voltage on the
device, while the minimum output voltage is limited to
the min duty cycle specification in the DC operating
characteristics section.
When the 0% duty cycle mode is selected, the
maximum duty cycle is limited to the max duty cycle
specification in the DC operating characteristics
section.
POWER-ON/OFF CONTROL
Sequencing can be initiated: automatically, by a
volatile I2C Power on command, or by asserting the
PWREN pin. When the PWREN pin is programmed to
initiate sequencing, it can be level or edge triggered.
The PWREN input has a programmable de-bounce
time of 100, 50, or 25ms. The de-bounce time can also
be disabled.
Figure 5 – Power on sequencing waveforms.
Time = 4ms/devision, Scale = 1V/devision
Ch 1 = 3.3V output (Yellow trace)
Ch 2 = 2.5V output (Blue trace)
Ch 3 = 1.8V output (Purple trace)
Ch 4 = 1.2V output (Green trace)
When configured as a push-button enable, PWREN
must be asserted longer than the de-bounce time
before sequencing can commence, and pulled low for
the same period to disable the channels.
POWER ON/OFF DELAY
There is a programmable delay between when
channels in subsequent sequence positions are
enabled. The delay is programmable at 50, 25, 12.5
and 1.5ms intervals. This delay is programmable for
ENABLE
Each output can be enabled and disable by an enable
each
of
the
four
sequence
positions.
signal. The enable signal is can be provided from
Summit Microelectronics, Inc
2111 2.4 6/24/2008
16
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
